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ath9k_hw: add register definitions related to PA predistortion
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
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Felix Fietkau authored and John W. Linville committed Jun 14, 2010
1 parent 96d159d commit ab33449
Showing 1 changed file with 207 additions and 17 deletions.
224 changes: 207 additions & 17 deletions drivers/net/wireless/ath/ath9k/ar9003_phy.h
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Original file line number Diff line number Diff line change
Expand Up @@ -459,7 +459,11 @@
#define AR_PHY_TSTDAC (AR_SM_BASE + 0x168)

#define AR_PHY_CHAN_STATUS (AR_SM_BASE + 0x16c)
#define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + 0x170)

#define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + 0x170)
#define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ 0x00000008
#define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S 3

#define AR_PHY_CHNINFO_NOISEPWR (AR_SM_BASE + 0x174)
#define AR_PHY_CHNINFO_GAINDIFF (AR_SM_BASE + 0x178)
#define AR_PHY_CHNINFO_FINETIM (AR_SM_BASE + 0x17c)
Expand All @@ -475,17 +479,63 @@
#define AR_PHY_PWRTX_MAX (AR_SM_BASE + 0x1f0)
#define AR_PHY_POWER_TX_SUB (AR_SM_BASE + 0x1f4)

#define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204)
#define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208)
#define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c)
#define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220)
#define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c)
#define AR_PHY_TPC_19 (AR_SM_BASE + 0x240)
#define AR_PHY_TPC_1 (AR_SM_BASE + 0x1f8)
#define AR_PHY_TPC_1_FORCED_DAC_GAIN 0x0000003e
#define AR_PHY_TPC_1_FORCED_DAC_GAIN_S 1
#define AR_PHY_TPC_1_FORCE_DAC_GAIN 0x00000001
#define AR_PHY_TPC_1_FORCE_DAC_GAIN_S 0

#define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204)
#define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208)
#define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c)

#define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220)
#define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
#define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
#define AR_PHY_TPC_11_OLPC_GAIN_DELTA 0x00ff0000
#define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S 16

#define AR_PHY_TPC_12 (AR_SM_BASE + 0x224)
#define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5 0x3e000000
#define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S 25

#define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c)
#define AR_PHY_TPC_18_THERM_CAL_VALUE 0x000000ff
#define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
#define AR_PHY_TPC_18_VOLT_CAL_VALUE 0x0000ff00
#define AR_PHY_TPC_18_VOLT_CAL_VALUE_S 8

#define AR_PHY_TPC_19 (AR_SM_BASE + 0x240)
#define AR_PHY_TPC_19_ALPHA_VOLT 0x001f0000
#define AR_PHY_TPC_19_ALPHA_VOLT_S 16
#define AR_PHY_TPC_19_ALPHA_THERM 0xff
#define AR_PHY_TPC_19_ALPHA_THERM_S 0

#define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258)
#define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN 0x00000001
#define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S 0
#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN 0x0000000e
#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_S 1
#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN 0x00000030
#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_S 4
#define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN 0x000003c0
#define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN_S 6
#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA 0x00003c00
#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA_S 10
#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB 0x0003c000
#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB_S 14
#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC 0x003c0000
#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC_S 18
#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND 0x00c00000
#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND_S 22
#define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL 0x01000000
#define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL_S 24

#define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258)

#define AR_PHY_PDADC_TAB_0 (AR_SM_BASE + 0x280)

#define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)

#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + 0x448)
#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + 0x440)
#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c)
Expand All @@ -498,7 +548,17 @@
#define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0)
#define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4)
#define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc)
#define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248)

#define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248)
#define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0

#define AR_PHY_BB_THERM_ADC_4 (AR_SM_BASE + 0x254)
#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE 0x000000ff
#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S 0
#define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE 0x0000ff00
#define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S 8


#define AR_PHY_65NM_CH0_SYNTH4 0x1608c
#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002
Expand Down Expand Up @@ -668,17 +728,9 @@
#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x00003fff
#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0

#define AR_PHY_TPC_18_THERM_CAL_VALUE 0xff
#define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
#define AR_PHY_TPC_19_ALPHA_THERM 0xff
#define AR_PHY_TPC_19_ALPHA_THERM_S 0

#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28

#define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0

/*
* Channel 1 Register Map
*/
Expand Down Expand Up @@ -850,6 +902,144 @@

#define AR_PHY_WATCHDOG_STATUS_CLR 0x00000008

/*
* PAPRD registers
*/
#define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)

#define AR_PHY_PAPRD_AM2AM (AR_CHAN_BASE + 0xe4)
#define AR_PHY_PAPRD_AM2AM_MASK 0x01ffffff
#define AR_PHY_PAPRD_AM2AM_MASK_S 0

#define AR_PHY_PAPRD_AM2PM (AR_CHAN_BASE + 0xe8)
#define AR_PHY_PAPRD_AM2PM_MASK 0x01ffffff
#define AR_PHY_PAPRD_AM2PM_MASK_S 0

#define AR_PHY_PAPRD_HT40 (AR_CHAN_BASE + 0xec)
#define AR_PHY_PAPRD_HT40_MASK 0x01ffffff
#define AR_PHY_PAPRD_HT40_MASK_S 0

#define AR_PHY_PAPRD_CTRL0_B0 (AR_CHAN_BASE + 0xf0)
#define AR_PHY_PAPRD_CTRL0_B1 (AR_CHAN1_BASE + 0xf0)
#define AR_PHY_PAPRD_CTRL0_B2 (AR_CHAN2_BASE + 0xf0)
#define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE 0x00000001
#define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE_S 0
#define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK 0x00000002
#define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK_S 1
#define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH 0xf8000000
#define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S 27

#define AR_PHY_PAPRD_CTRL1_B0 (AR_CHAN_BASE + 0xf4)
#define AR_PHY_PAPRD_CTRL1_B1 (AR_CHAN1_BASE + 0xf4)
#define AR_PHY_PAPRD_CTRL1_B2 (AR_CHAN2_BASE + 0xf4)
#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA 0x00000001
#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA_S 0
#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE 0x00000002
#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE_S 1
#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE 0x00000004
#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE_S 2
#define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL 0x000001f8
#define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_S 3
#define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK 0x0001fe00
#define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK_S 9
#define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT 0x0ffe0000
#define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S 17

#define AR_PHY_PAPRD_TRAINER_CNTL1 (AR_SM_BASE + 0x490)
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 0x00000001
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x0000007e
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_S 1
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE 0x00000100
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_S 8
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE 0x00000200
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_S 9
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE 0x00000400
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_S 10
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE 0x00000800
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_S 11
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x0003f000
#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 12

#define AR_PHY_PAPRD_TRAINER_CNTL2 (AR_SM_BASE + 0x494)
#define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF
#define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0

#define AR_PHY_PAPRD_TRAINER_CNTL3 (AR_SM_BASE + 0x498)
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x0000003f
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x00000fc0
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_S 6
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL 0x0001f000
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_S 12
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES 0x000e0000
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_S 17
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN 0x00f00000
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S 20
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN 0x0f000000
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_S 24
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 0x20000000
#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 29

#define AR_PHY_PAPRD_TRAINER_CNTL4 (AR_SM_BASE + 0x49c)
#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x03ff0000
#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16
#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0x0000f000
#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_S 12
#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR 0x00000fff
#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S 0

#define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0 (AR_CHAN_BASE + 0x100)
#define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0 (AR_CHAN_BASE + 0x104)
#define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0 (AR_CHAN_BASE + 0x108)
#define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0 (AR_CHAN_BASE + 0x10c)
#define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0 (AR_CHAN_BASE + 0x110)
#define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0 (AR_CHAN_BASE + 0x114)
#define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0 (AR_CHAN_BASE + 0x118)
#define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0 (AR_CHAN_BASE + 0x11c)
#define AR_PHY_PAPRD_PRE_POST_SCALING 0x3FFFF
#define AR_PHY_PAPRD_PRE_POST_SCALING_S 0

#define AR_PHY_PAPRD_TRAINER_STAT1 (AR_SM_BASE + 0x4a0)
#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE 0x00000001
#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S 0
#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE 0x00000002
#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_S 1
#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR 0x00000004
#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_S 2
#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE 0x00000008
#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_S 3
#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX 0x000001f0
#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_S 4
#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR 0x0001fe00
#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_S 9

#define AR_PHY_PAPRD_TRAINER_STAT2 (AR_SM_BASE + 0x4a4)
#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL 0x0000ffff
#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S 0
#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX 0x001f0000
#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_S 16
#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX 0x00600000
#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_S 21

#define AR_PHY_PAPRD_TRAINER_STAT3 (AR_SM_BASE + 0x4a8)
#define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT 0x000fffff
#define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S 0

#define AR_PHY_PAPRD_MEM_TAB_B0 (AR_CHAN_BASE + 0x120)
#define AR_PHY_PAPRD_MEM_TAB_B1 (AR_CHAN1_BASE + 0x120)
#define AR_PHY_PAPRD_MEM_TAB_B2 (AR_CHAN2_BASE + 0x120)

#define AR_PHY_PA_GAIN123_B0 (AR_CHAN_BASE + 0xf8)
#define AR_PHY_PA_GAIN123_B1 (AR_CHAN1_BASE + 0xf8)
#define AR_PHY_PA_GAIN123_B2 (AR_CHAN2_BASE + 0xf8)
#define AR_PHY_PA_GAIN123_PA_GAIN1 0x3FF
#define AR_PHY_PA_GAIN123_PA_GAIN1_S 0

#define AR_PHY_POWERTX_RATE5 (AR_SM_BASE + 0x1d0)
#define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F
#define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 0

void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);

#endif /* AR9003_PHY_H */

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