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OMAP: DSS2: Add new registers for NV12 support
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Add new registers specific to UV color component that are introduced in OMAP4.
Add simple helper functions to configure the newly added registers.
These new registers are mainly:
- UV base address registers used specifically for NV12 color-format
- FIR registers used for UV-color-component scaling on OMAP4
- Accumulator registers used for UV-color-component scaling
Add these new registers to save/restore and DUMPREG functions.
Also add two new features for OMAP4:
- FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires
  separate handling.
- FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register.

Signed-off-by: Amber Jain <amber@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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Amber Jain authored and Tomi Valkeinen committed May 23, 2011
1 parent 5719d35 commit ab5ca07
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Showing 4 changed files with 349 additions and 2 deletions.
197 changes: 197 additions & 0 deletions drivers/video/omap2/dss/dispc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -217,6 +217,25 @@ void dispc_save_context(void)
for (i = 0; i < 8; i++)
SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));

if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
SR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
SR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
SR(OVL_FIR2(OMAP_DSS_VIDEO1));
SR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
SR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));

for (i = 0; i < 8; i++)
SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));

for (i = 0; i < 8; i++)
SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));

for (i = 0; i < 8; i++)
SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
}
if (dss_has_feature(FEAT_ATTR2))
SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));

SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));

/* VID2 */
Expand Down Expand Up @@ -245,6 +264,25 @@ void dispc_save_context(void)
for (i = 0; i < 8; i++)
SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));

if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
SR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
SR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
SR(OVL_FIR2(OMAP_DSS_VIDEO2));
SR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
SR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));

for (i = 0; i < 8; i++)
SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));

for (i = 0; i < 8; i++)
SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));

for (i = 0; i < 8; i++)
SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
}
if (dss_has_feature(FEAT_ATTR2))
SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));

SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));

if (dss_has_feature(FEAT_CORE_CLK_DIV))
Expand Down Expand Up @@ -338,6 +376,25 @@ void dispc_restore_context(void)
for (i = 0; i < 8; i++)
RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));

if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
RR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
RR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
RR(OVL_FIR2(OMAP_DSS_VIDEO1));
RR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
RR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));

for (i = 0; i < 8; i++)
RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));

for (i = 0; i < 8; i++)
RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));

for (i = 0; i < 8; i++)
RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
}
if (dss_has_feature(FEAT_ATTR2))
RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));

RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));

/* VID2 */
Expand Down Expand Up @@ -366,6 +423,25 @@ void dispc_restore_context(void)
for (i = 0; i < 8; i++)
RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));

if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
RR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
RR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
RR(OVL_FIR2(OMAP_DSS_VIDEO2));
RR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
RR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));

for (i = 0; i < 8; i++)
RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));

for (i = 0; i < 8; i++)
RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));

for (i = 0; i < 8; i++)
RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
}
if (dss_has_feature(FEAT_ATTR2))
RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));

RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));

if (dss_has_feature(FEAT_CORE_CLK_DIV))
Expand Down Expand Up @@ -476,6 +552,27 @@ static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
}

static void _dispc_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
{
BUG_ON(plane == OMAP_DSS_GFX);

dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
}

static void _dispc_write_firhv2_reg(enum omap_plane plane, int reg, u32 value)
{
BUG_ON(plane == OMAP_DSS_GFX);

dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
}

static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
{
BUG_ON(plane == OMAP_DSS_GFX);

dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
}

static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
int vscaleup, int five_taps)
{
Expand Down Expand Up @@ -645,6 +742,16 @@ static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
}

static void _dispc_set_plane_ba0_uv(enum omap_plane plane, u32 paddr)
{
dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
}

static void _dispc_set_plane_ba1_uv(enum omap_plane plane, u32 paddr)
{
dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
}

static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
{
u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
Expand Down Expand Up @@ -1025,6 +1132,21 @@ static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
}

static void _dispc_set_vid_accu2_0(enum omap_plane plane, int haccu, int vaccu)
{
u32 val;

val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
}

static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
{
u32 val;

val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
}

static void _dispc_set_scaling(enum omap_plane plane,
u16 orig_width, u16 orig_height,
Expand Down Expand Up @@ -2496,6 +2618,44 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));

if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO1));
DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO1));
DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO1));
DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO1));
DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO1));

DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 0));
DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 1));
DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 2));
DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 3));
DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 4));
DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 5));
DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 6));
DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 7));

DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 0));
DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 1));
DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 2));
DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 3));
DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 4));
DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 5));
DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 6));
DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 7));

DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 0));
DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 1));
DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 2));
DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 3));
DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 4));
DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 5));
DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 6));
DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 7));
}
if (dss_has_feature(FEAT_ATTR2))
DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));


DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
Expand Down Expand Up @@ -2526,6 +2686,43 @@ void dispc_dump_regs(struct seq_file *s)
DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));

if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO2));
DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO2));
DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO2));
DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO2));
DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO2));

DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 0));
DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 1));
DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 2));
DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 3));
DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 4));
DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 5));
DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 6));
DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 7));

DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 0));
DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 1));
DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 2));
DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 3));
DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 4));
DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 5));
DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 6));
DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 7));

DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 0));
DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 1));
DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 2));
DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 3));
DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 4));
DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 5));
DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 6));
DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 7));
}
if (dss_has_feature(FEAT_ATTR2))
DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));

DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));

Expand Down
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