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ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi
No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren
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Jan 28, 2013
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Original file line number | Diff line number | Diff line change |
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@@ -90,7 +90,6 @@ | |
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serial@70006000 { | ||
status = "okay"; | ||
clock-frequency = <408000000>; | ||
}; | ||
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i2c@7000c000 { | ||
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