---

yaml
---
r: 331389
b: refs/heads/master
c: 54d69df
h: refs/heads/master
i:
  331387: eefd228
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 46f2007c1efadfa4071c17e75f140c47f09293de
+refs/heads/master: 54d69df5849ec2e660aa12ac75562618c10fb499

trunk/arch/arm/mach-omap1/devices.c

@@ -357,6 +357,33 @@ static inline void omap_init_uwire(void) {}
 #endif
 
 
+#define OMAP1_RNG_BASE		0xfffe5000
+
+static struct resource omap1_rng_resources[] = {
+	{
+		.start		= OMAP1_RNG_BASE,
+		.end		= OMAP1_RNG_BASE + 0x4f,
+		.flags		= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device omap1_rng_device = {
+	.name		= "omap_rng",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(omap1_rng_resources),
+	.resource	= omap1_rng_resources,
+};
+
+static void omap1_init_rng(void)
+{
+	if (!cpu_is_omap16xx())
+		return;
+
+	(void) platform_device_register(&omap1_rng_device);
+}
+
+/*-------------------------------------------------------------------------*/
+
 /*
  * This gets called after board-specific INIT_MACHINE, and initializes most
  * on-chip peripherals accessible on this board (except for few like USB):
@@ -395,6 +422,7 @@ static int __init omap1_init_devices(void)
 	omap_init_spi100k();
 	omap_init_sti();
 	omap_init_uwire();
+	omap1_init_rng();
 
 	return 0;
 }

trunk/arch/arm/mach-omap1/timer.c

@@ -141,7 +141,7 @@ static int __init omap1_dm_timer_init(void)
 
 		pdata->set_timer_src = omap1_dm_timer_set_src;
 		pdata->timer_capability = OMAP_TIMER_ALWON |
-				OMAP_TIMER_NEEDS_RESET;
+				OMAP_TIMER_NEEDS_RESET | OMAP_TIMER_HAS_DSP_IRQ;
 
 		ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
 		if (ret) {

trunk/arch/arm/mach-omap2/Makefile

@@ -179,6 +179,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= omap_hwmod_44xx_data.o
 
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)			+= emu.o
+obj-$(CONFIG_HW_PERF_EVENTS)		+= pmu.o
 
 # L3 interconnect
 obj-$(CONFIG_ARCH_OMAP3)		+= omap_l3_smx.o

trunk/arch/arm/mach-omap2/board-apollon.c

@@ -202,7 +202,7 @@ static inline void __init apollon_init_smc91x(void)
 		return;
 	}
 
-	clk_enable(gpmc_fck);
+	clk_prepare_enable(gpmc_fck);
 	rate = clk_get_rate(gpmc_fck);
 
 	eth_cs = APOLLON_ETH_CS;
@@ -246,7 +246,7 @@ static inline void __init apollon_init_smc91x(void)
 		gpmc_cs_free(APOLLON_ETH_CS);
 	}
 out:
-	clk_disable(gpmc_fck);
+	clk_disable_unprepare(gpmc_fck);
 	clk_put(gpmc_fck);
 }
 

trunk/arch/arm/mach-omap2/board-h4.c

@@ -265,9 +265,9 @@ static inline void __init h4_init_debug(void)
 		return;
 	}
 
-	clk_enable(gpmc_fck);
+	clk_prepare_enable(gpmc_fck);
 	rate = clk_get_rate(gpmc_fck);
-	clk_disable(gpmc_fck);
+	clk_disable_unprepare(gpmc_fck);
 	clk_put(gpmc_fck);
 
 	if (is_gpmc_muxed())
@@ -311,7 +311,7 @@ static inline void __init h4_init_debug(void)
 		gpmc_cs_free(eth_cs);
 
 out:
-	clk_disable(gpmc_fck);
+	clk_disable_unprepare(gpmc_fck);
 	clk_put(gpmc_fck);
 }
 

trunk/arch/arm/mach-omap2/board-omap4panda.c

@@ -171,7 +171,7 @@ static void __init omap4_ehci_init(void)
 		return;
 	}
 	clk_set_rate(phy_ref_clk, 19200000);
-	clk_enable(phy_ref_clk);
+	clk_prepare_enable(phy_ref_clk);
 
 	/* disable the power to the usb hub prior to init and reset phy+hub */
 	ret = gpio_request_array(panda_ehci_gpios,

trunk/arch/arm/mach-omap2/clkt2xxx_apll.c

@@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
 	omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 
 	omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
-			     OMAP24XX_CM_IDLEST_VAL, clk->name);
+			     OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
 
 	/*
 	 * REVISIT: Should we return an error code if omap2_wait_clock_ready()

trunk/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c

@@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
 long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 {
 	const struct prcm_config *ptr;
-	long highest_rate;
+	long highest_rate, sys_clk_rate;
 
 	highest_rate = -EINVAL;
+	sys_clk_rate = __clk_get_rate(sclk);
 
 	for (ptr = rate_table; ptr->mpu_speed; ptr++) {
 		if (!(ptr->flags & cpu_mask))
 			continue;
-		if (ptr->xtal_speed != sclk->rate)
+		if (ptr->xtal_speed != sys_clk_rate)
 			continue;
 
 		highest_rate = ptr->mpu_speed;
@@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 	const struct prcm_config *prcm;
 	unsigned long found_speed = 0;
 	unsigned long flags;
+	long sys_clk_rate;
+
+	sys_clk_rate = __clk_get_rate(sclk);
 
 	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 		if (!(prcm->flags & cpu_mask))
 			continue;
 
-		if (prcm->xtal_speed != sclk->rate)
+		if (prcm->xtal_speed != sys_clk_rate)
 			continue;
 
 		if (prcm->mpu_speed <= rate) {

trunk/arch/arm/mach-omap2/clkt34xx_dpll3m2.c

@@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 	struct omap_sdrc_params *sdrc_cs0;
 	struct omap_sdrc_params *sdrc_cs1;
 	int ret;
+	unsigned long clkrate;
 
 	if (!clk || !rate)
 		return -EINVAL;
@@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 	if (validrate != rate)
 		return -EINVAL;
 
-	sdrcrate = sdrc_ick_p->rate;
-	if (rate > clk->rate)
-		sdrcrate <<= ((rate / clk->rate) >> 1);
+	sdrcrate = __clk_get_rate(sdrc_ick_p);
+	clkrate = __clk_get_rate(clk);
+	if (rate > clkrate)
+		sdrcrate <<= ((rate / clkrate) >> 1);
 	else
-		sdrcrate >>= ((clk->rate / rate) >> 1);
+		sdrcrate >>= ((clkrate / rate) >> 1);
 
 	ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
 	if (ret)
@@ -82,16 +84,16 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 	/*
 	 * XXX This only needs to be done when the CPU frequency changes
 	 */
-	_mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+	_mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
 	c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
 	c += 1;  /* for safety */
 	c *= SDRC_MPURATE_LOOPS;
 	c >>= SDRC_MPURATE_SCALE;
 	if (c == 0)
 		c = 1;
 
-	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
-		 validrate);
+	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
+		 clkrate, validrate);
 	pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
 		 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 		 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
@@ -102,14 +104,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 
 	if (sdrc_cs1)
 		omap3_configure_core_dpll(
-				  new_div, unlock_dll, c, rate > clk->rate,
+				  new_div, unlock_dll, c, rate > clkrate,
 				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
 				  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
 				  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
 	else
 		omap3_configure_core_dpll(
-				  new_div, unlock_dll, c, rate > clk->rate,
+				  new_div, unlock_dll, c, rate > clkrate,
 				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
 				  0, 0, 0, 0);