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Russell King
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--- | ||
refs/heads/master: a06f916b7a9b57447ceb875eb0a89f1a66b31bca | ||
refs/heads/master: 06afb1a087d49ae0f676b2e5b9ffe5f4b3aba355 |
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What: /sys/class/scsi_host/hostX/isci_id | ||
Date: June 2011 | ||
Contact: Dave Jiang <dave.jiang@intel.com> | ||
Description: | ||
This file contains the enumerated host ID for the Intel | ||
SCU controller. The Intel(R) C600 Series Chipset SATA/SAS | ||
Storage Control Unit embeds up to two 4-port controllers in | ||
a single PCI device. The controllers are enumerated in order | ||
which usually means the lowest number scsi_host corresponds | ||
with the first controller, but this association is not | ||
guaranteed. The 'isci_id' attribute unambiguously identifies | ||
the controller index: '0' for the first controller, | ||
'1' for the second. |
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* ARM L2 Cache Controller | ||
|
||
ARM cores often have a separate level 2 cache controller. There are various | ||
implementations of the L2 cache controller with compatible programming models. | ||
The ARM L2 cache representation in the device tree should be done as follows: | ||
|
||
Required properties: | ||
|
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- compatible : should be one of: | ||
"arm,pl310-cache" | ||
"arm,l220-cache" | ||
"arm,l210-cache" | ||
- cache-unified : Specifies the cache is a unified cache. | ||
- cache-level : Should be set to 2 for a level 2 cache. | ||
- reg : Physical base address and size of cache controller's memory mapped | ||
registers. | ||
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Optional properties: | ||
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- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of | ||
read, write and setup latencies. Minimum valid values are 1. Controllers | ||
without setup latency control should use a value of 0. | ||
- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of | ||
read, write and setup latencies. Controllers without setup latency control | ||
should use 0. Controllers without separate read and write Tag RAM latency | ||
values should only use the first cell. | ||
- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. | ||
- arm,filter-ranges : <start length> Starting address and length of window to | ||
filter. Addresses in the filter window are directed to the M1 port. Other | ||
addresses will go to the M0 port. | ||
- interrupts : 1 combined interrupt. | ||
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||
Example: | ||
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L2: cache-controller { | ||
compatible = "arm,pl310-cache"; | ||
reg = <0xfff12000 0x1000>; | ||
arm,data-latency = <1 1 1>; | ||
arm,tag-latency = <2 2 2>; | ||
arm,filter-latency = <0x80000000 0x8000000>; | ||
cache-unified; | ||
cache-level = <2>; | ||
interrupts = <45>; | ||
}; |
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