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yaml --- r: 148547 b: refs/heads/master c: c8f36dc h: refs/heads/master i: 148545: b4d784f 148543: 7f3de34 v: v3
git-mirror · Jun 12, 2009 · ac7d8b5 · ac7d8b5
1 parent 3e6ffff
commit ac7d8b5
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Showing 3 changed files with 34 additions and 379 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: b9ccf14bc5352b86e7e254e6cf55d9b917b1b1cc
+refs/heads/master: c8f36dc3c11c3e9e879ded82cdf5d748d4ab2fb2
diff --git a/trunk/arch/blackfin/mach-bf561/Kconfig b/trunk/arch/blackfin/mach-bf561/Kconfig
@@ -9,22 +9,9 @@ if (!SMP)
 comment "Core B Support"
 
 config BF561_COREB
-	bool "Enable Core B support"
+	bool "Enable Core B loader"
 	default y
 
-config BF561_COREB_RESET
-	bool "Enable Core B reset support"
-	default n
-	help
-	  This requires code in the application that is loaded
-	  into Core B. In order to reset, the application needs
-	  to install an interrupt handler for Supplemental
-	  Interrupt 0, that sets RETI to 0xff600000 and writes
-	  bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0.
-	  This causes Core B to stall when Supplemental Interrupt
-	  0 is set, and will reset PC to 0xff600000 when
-	  COREB_SRAM_INIT is cleared.
-
 endif
 
 comment "Interrupt Priority Assignment"