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yaml
---
r: 148562
b: refs/heads/master
c: 8af7ffa
h: refs/heads/master
v: v3
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Graf Yang authored and Mike Frysinger committed Jun 12, 2009
1 parent 199b9da commit ace7cb1
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Showing 2 changed files with 9 additions and 2 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: 1fa9be72b558c39459f98835eb86dbb4ef4da30b
refs/heads/master: 8af7ffa0d5460586e0f06b2f045a6a2631224b61
9 changes: 8 additions & 1 deletion trunk/arch/blackfin/kernel/cplb-nompu/cacheinit.c
Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,14 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
}

ctrl = bfin_read_DMEM_CONTROL();
ctrl |= DMEM_CNTR;

/*
* Anomaly notes:
* 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
* register, so that the port preferences for DAG0 and DAG1 are set
* to port B
*/
ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);
bfin_write_DMEM_CONTROL(ctrl);
SSYNC();
}
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