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yaml
---
r: 201515
b: refs/heads/master
c: 21f0ba9
h: refs/heads/master
i:
  201513: be2ad50
  201511: 856e03a
v: v3
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Olaf Rempel authored and Nicolas Pitre committed Jul 17, 2010
1 parent ea5a1b4 commit ada3151
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Showing 2 changed files with 35 additions and 1 deletion.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: 6f2b186a0f1e70be411ca260d4577f1ed35d58e0
refs/heads/master: 21f0ba90a447090153edeaf2f14f9f7e8bd9bc80
34 changes: 34 additions & 0 deletions trunk/arch/arm/plat-orion/pcie.c
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@
#include <linux/mbus.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include <linux/delay.h>

/*
* PCIe unit register offsets.
Expand Down Expand Up @@ -46,6 +47,8 @@
#define PCIE_STAT_BUS_OFFS 8
#define PCIE_STAT_BUS_MASK 0xff
#define PCIE_STAT_LINK_DOWN 1
#define PCIE_DEBUG_CTRL 0x1a60
#define PCIE_DEBUG_SOFT_RESET (1<<20)


u32 __init orion_pcie_dev_id(void __iomem *base)
Expand Down Expand Up @@ -85,6 +88,32 @@ void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
writel(stat, base + PCIE_STAT_OFF);
}

void __init orion_pcie_reset(void __iomem *base)
{
u32 reg;
int i;

/*
* MV-S104860-U0, Rev. C:
* PCI Express Unit Soft Reset
* When set, generates an internal reset in the PCI Express unit.
* This bit should be cleared after the link is re-established.
*/
reg = readl(base + PCIE_DEBUG_CTRL);
reg |= PCIE_DEBUG_SOFT_RESET;
writel(reg, base + PCIE_DEBUG_CTRL);

for (i = 0; i < 20; i++) {
mdelay(10);

if (orion_pcie_link_up(base))
break;
}

reg &= ~(PCIE_DEBUG_SOFT_RESET);
writel(reg, base + PCIE_DEBUG_CTRL);
}

/*
* Setup PCIE BARs and Address Decode Wins:
* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
Expand Down Expand Up @@ -152,6 +181,11 @@ void __init orion_pcie_setup(void __iomem *base,
u16 cmd;
u32 mask;

/*
* soft reset PCIe unit
*/
orion_pcie_reset(base);

/*
* Point PCIe unit MBUS decode windows to DRAM space.
*/
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