---

yaml
---
r: 100751
b: refs/heads/master
c: 777f9be
h: refs/heads/master
i:
  100749: 488332c
  100747: 9d6acf8
  100743: c2ce3e6
  100735: a9544d8
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 1219715de70956557b9dedf3ee021a73d4f4ec52
+refs/heads/master: 777f9bebad3476b7dbf5cd8abbd3414139ca0e48

trunk/arch/arm/Kconfig

@@ -370,6 +370,14 @@ config ARCH_NS9XXX
 
 	  <http://www.digi.com/products/microprocessors/index.jsp>
 
+config ARCH_LOKI
+	bool "Marvell Loki (88RC8480)"
+	select GENERIC_TIME
+	select GENERIC_CLOCKEVENTS
+	select PLAT_ORION
+	help
+	  Support for the Marvell Loki (88RC8480) SoC.
+
 config ARCH_MXC
 	bool "Freescale MXC/iMX-based"
 	select ARCH_MTD_XIP
@@ -508,6 +516,8 @@ source "arch/arm/mach-ixp2000/Kconfig"
 
 source "arch/arm/mach-ixp23xx/Kconfig"
 
+source "arch/arm/mach-loki/Kconfig"
+
 source "arch/arm/mach-pxa/Kconfig"
 
 source "arch/arm/mach-sa1100/Kconfig"

trunk/arch/arm/Makefile

@@ -140,6 +140,7 @@ endif
  machine-$(CONFIG_ARCH_MX3)	   := mx3
  machine-$(CONFIG_ARCH_ORION5X)	   := orion5x
  machine-$(CONFIG_ARCH_MSM7X00A)   := msm
+ machine-$(CONFIG_ARCH_LOKI)       := loki
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.

trunk/arch/arm/mach-loki/Kconfig

@@ -0,0 +1,13 @@
+if ARCH_LOKI
+
+menu "Marvell Loki (88RC8480) Implementations"
+
+config MACH_LB88RC8480
+	bool "Marvell LB88RC8480 Development Board"
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell LB88RC8480 Development Board.
+
+endmenu
+
+endif

trunk/arch/arm/mach-loki/Makefile

@@ -0,0 +1,3 @@
+obj-y				+= common.o addr-map.o irq.o
+
+obj-$(CONFIG_MACH_LB88RC8480)	+= lb88rc8480-setup.o

trunk/arch/arm/mach-loki/Makefile.boot

@@ -0,0 +1,3 @@
+   zreladdr-y	:= 0x00008000
+params_phys-y	:= 0x00000100
+initrd_phys-y	:= 0x00800000

trunk/arch/arm/mach-loki/addr-map.c

@@ -0,0 +1,121 @@
+/*
+ * arch/arm/mach-loki/addr-map.c
+ *
+ * Address map functions for Marvell Loki (88RC8480) SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include "common.h"
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define TARGET_DDR		0
+#define TARGET_DEV_BUS		1
+#define TARGET_PCIE0		3
+#define TARGET_PCIE1		4
+#define ATTR_DEV_BOOT		0x0f
+#define ATTR_DEV_CS2		0x1b
+#define ATTR_DEV_CS1		0x1d
+#define ATTR_DEV_CS0		0x1e
+#define ATTR_PCIE_IO		0x51
+#define ATTR_PCIE_MEM		0x59
+
+/*
+ * Helpers to get DDR bank info
+ */
+#define DDR_SIZE_CS(n)		DDR_REG(0x1500 + ((n) << 3))
+#define DDR_BASE_CS(n)		DDR_REG(0x1504 + ((n) << 3))
+
+/*
+ * CPU Address Decode Windows registers
+ */
+#define CPU_WIN_CTRL(n)		BRIDGE_REG(0x000 | ((n) << 4))
+#define CPU_WIN_BASE(n)		BRIDGE_REG(0x004 | ((n) << 4))
+#define CPU_WIN_REMAP_LO(n)	BRIDGE_REG(0x008 | ((n) << 4))
+#define CPU_WIN_REMAP_HI(n)	BRIDGE_REG(0x00c | ((n) << 4))
+
+
+struct mbus_dram_target_info loki_mbus_dram_info;
+
+static void __init setup_cpu_win(int win, u32 base, u32 size,
+				 u8 target, u8 attr, int remap)
+{
+	u32 ctrl;
+
+	base &= 0xffff0000;
+	ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (1 << 5) | target;
+
+	writel(base, CPU_WIN_BASE(win));
+	writel(ctrl, CPU_WIN_CTRL(win));
+	if (win < 2) {
+		if (remap < 0)
+			remap = base;
+
+		writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
+		writel(0, CPU_WIN_REMAP_HI(win));
+	}
+}
+
+void __init loki_setup_cpu_mbus(void)
+{
+	int i;
+	int cs;
+
+	/*
+	 * First, disable and clear windows.
+	 */
+	for (i = 0; i < 8; i++) {
+		writel(0, CPU_WIN_BASE(i));
+		writel(0, CPU_WIN_CTRL(i));
+		if (i < 2) {
+			writel(0, CPU_WIN_REMAP_LO(i));
+			writel(0, CPU_WIN_REMAP_HI(i));
+		}
+	}
+
+	/*
+	 * Setup windows for PCIe IO+MEM space.
+	 */
+	setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE,
+		      TARGET_PCIE0, ATTR_PCIE_MEM, -1);
+	setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE,
+		      TARGET_PCIE1, ATTR_PCIE_MEM, -1);
+
+	/*
+	 * Setup MBUS dram target info.
+	 */
+	loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+	for (i = 0, cs = 0; i < 4; i++) {
+		u32 base = readl(DDR_BASE_CS(i));
+		u32 size = readl(DDR_SIZE_CS(i));
+
+		/*
+		 * Chip select enabled?
+		 */
+		if (size & 1) {
+			struct mbus_dram_window *w;
+
+			w = &loki_mbus_dram_info.cs[cs++];
+			w->cs_index = i;
+			w->mbus_attr = 0xf & ~(1 << i);
+			w->base = base & 0xffff0000;
+			w->size = (size | 0x0000ffff) + 1;
+		}
+	}
+	loki_mbus_dram_info.num_cs = cs;
+}
+
+void __init loki_setup_dev_boot_win(u32 base, u32 size)
+{
+	setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
+}