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yaml
---
r: 133653
b: refs/heads/master
c: 9962d03
h: refs/heads/master
i:
  133651: e6c846e
v: v3
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Alexander Graf authored and Avi Kivity committed Mar 24, 2009
1 parent 0ae87ac commit b059e7d
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Showing 6 changed files with 13 additions and 9 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: f0b85051d0f0891378a83db22c0786f1d756fbff
refs/heads/master: 9962d032bbff0268f22068787831405f8468c8b4
1 change: 1 addition & 0 deletions trunk/arch/x86/include/asm/kvm_host.h
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Expand Up @@ -22,6 +22,7 @@
#include <asm/pvclock-abi.h>
#include <asm/desc.h>
#include <asm/mtrr.h>
#include <asm/msr-index.h>

#define KVM_MAX_VCPUS 16
#define KVM_MEMORY_SLOTS 32
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7 changes: 7 additions & 0 deletions trunk/arch/x86/include/asm/msr-index.h
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Expand Up @@ -18,11 +18,13 @@
#define _EFER_LME 8 /* Long mode enable */
#define _EFER_LMA 10 /* Long mode active (read-only) */
#define _EFER_NX 11 /* No execute enable */
#define _EFER_SVME 12 /* Enable virtualization */

#define EFER_SCE (1<<_EFER_SCE)
#define EFER_LME (1<<_EFER_LME)
#define EFER_LMA (1<<_EFER_LMA)
#define EFER_NX (1<<_EFER_NX)
#define EFER_SVME (1<<_EFER_SVME)

/* Intel MSRs. Some also available on other CPUs */
#define MSR_IA32_PERFCTR0 0x000000c1
Expand Down Expand Up @@ -360,4 +362,9 @@
#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c

/* AMD-V MSRs */

#define MSR_VM_CR 0xc0010114
#define MSR_VM_HSAVE_PA 0xc0010117

#endif /* _ASM_X86_MSR_INDEX_H */
4 changes: 0 additions & 4 deletions trunk/arch/x86/include/asm/svm.h
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Expand Up @@ -174,10 +174,6 @@ struct __attribute__ ((__packed__)) vmcb {
#define SVM_CPUID_FEATURE_SHIFT 2
#define SVM_CPUID_FUNC 0x8000000a

#define MSR_EFER_SVME_MASK (1ULL << 12)
#define MSR_VM_CR 0xc0010114
#define MSR_VM_HSAVE_PA 0xc0010117ULL

#define SVM_VM_CR_SVM_DISABLE 4

#define SVM_SELECTOR_S_SHIFT 4
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2 changes: 1 addition & 1 deletion trunk/arch/x86/include/asm/virtext.h
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Expand Up @@ -118,7 +118,7 @@ static inline void cpu_svm_disable(void)

wrmsrl(MSR_VM_HSAVE_PA, 0);
rdmsrl(MSR_EFER, efer);
wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
wrmsrl(MSR_EFER, efer & ~EFER_SVME);
}

/** Makes sure SVM is disabled, if it is supported on the CPU
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6 changes: 3 additions & 3 deletions trunk/arch/x86/kvm/svm.c
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Expand Up @@ -198,7 +198,7 @@ static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
if (!npt_enabled && !(efer & EFER_LMA))
efer &= ~EFER_LME;

to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
vcpu->arch.shadow_efer = efer;
}

Expand Down Expand Up @@ -292,7 +292,7 @@ static void svm_hardware_enable(void *garbage)
svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);

rdmsrl(MSR_EFER, efer);
wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
wrmsrl(MSR_EFER, efer | EFER_SVME);

wrmsrl(MSR_VM_HSAVE_PA,
page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
Expand Down Expand Up @@ -559,7 +559,7 @@ static void init_vmcb(struct vcpu_svm *svm)
init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);

save->efer = MSR_EFER_SVME_MASK;
save->efer = EFER_SVME;
save->dr6 = 0xffff0ff0;
save->dr7 = 0x400;
save->rflags = 2;
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