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David Howells
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| Original file line number | Diff line number | Diff line change |
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| @@ -1,2 +1,2 @@ | ||
| --- | ||
| refs/heads/master: 9ee21723ccc30070f47c411826d4ed013cd050c2 | ||
| refs/heads/master: b75bb2365d50f73c09e42cf2de07f5805a3988ea |
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| /* MN10300 CPU core caching macros -*- asm -*- | ||
| * | ||
| * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| * Written by David Howells (dhowells@redhat.com) | ||
| * | ||
| * This program is free software; you can redistribute it and/or | ||
| * modify it under the terms of the GNU General Public Licence | ||
| * as published by the Free Software Foundation; either version | ||
| * 2 of the Licence, or (at your option) any later version. | ||
| */ | ||
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| ############################################################################### | ||
| # | ||
| # Invalidate the instruction cache. | ||
| # A0: Should hold CHCTR | ||
| # D0: Should have been read from CHCTR | ||
| # D1: Will be clobbered | ||
| # | ||
| # On some cores it is necessary to disable the icache whilst we do this. | ||
| # | ||
| ############################################################################### | ||
| .macro invalidate_icache,disable_irq | ||
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| #if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) | ||
| .if \disable_irq | ||
| # don't want an interrupt routine seeing a disabled cache | ||
| mov epsw,d1 | ||
| and ~EPSW_IE,epsw | ||
| or EPSW_NMID,epsw | ||
| nop | ||
| nop | ||
| .endif | ||
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| # disable the icache | ||
| and ~CHCTR_ICEN,d0 | ||
| movhu d0,(a0) | ||
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| # and wait for it to calm down | ||
| setlb | ||
| movhu (a0),d0 | ||
| btst CHCTR_ICBUSY,d0 | ||
| lne | ||
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| # invalidate | ||
| or CHCTR_ICINV,d0 | ||
| movhu d0,(a0) | ||
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| # wait for the cache to finish | ||
| setlb | ||
| movhu (a0),d0 | ||
| btst CHCTR_ICBUSY,d0 | ||
| lne | ||
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| # and reenable it | ||
| or CHCTR_ICEN,d0 | ||
| movhu d0,(a0) | ||
| movhu (a0),d0 | ||
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| .if \disable_irq | ||
| LOCAL_IRQ_RESTORE(d1) | ||
| .endif | ||
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| #else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ | ||
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| # invalidate | ||
| or CHCTR_ICINV,d0 | ||
| movhu d0,(a0) | ||
| movhu (a0),d0 | ||
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| #endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ | ||
| .endm | ||
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| ############################################################################### | ||
| # | ||
| # Invalidate the data cache. | ||
| # A0: Should hold CHCTR | ||
| # D0: Should have been read from CHCTR | ||
| # D1: Will be clobbered | ||
| # | ||
| # On some cores it is necessary to disable the dcache whilst we do this. | ||
| # | ||
| ############################################################################### | ||
| .macro invalidate_dcache,disable_irq | ||
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| #if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) | ||
| .if \disable_irq | ||
| # don't want an interrupt routine seeing a disabled cache | ||
| mov epsw,d1 | ||
| and ~EPSW_IE,epsw | ||
| or EPSW_NMID,epsw | ||
| nop | ||
| nop | ||
| .endif | ||
| # disable the dcache | ||
| and ~CHCTR_DCEN,d0 | ||
| movhu d0,(a0) | ||
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| # and wait for it to calm down | ||
| setlb | ||
| movhu (a0),d0 | ||
| btst CHCTR_DCBUSY,d0 | ||
| lne | ||
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| # invalidate | ||
| or CHCTR_DCINV,d0 | ||
| movhu d0,(a0) | ||
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| # wait for the cache to finish | ||
| setlb | ||
| movhu (a0),d0 | ||
| btst CHCTR_DCBUSY,d0 | ||
| lne | ||
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| # and reenable it | ||
| or CHCTR_DCEN,d0 | ||
| movhu d0,(a0) | ||
| movhu (a0),d0 | ||
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| .if \disable_irq | ||
| LOCAL_IRQ_RESTORE(d1) | ||
| .endif | ||
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| #else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ | ||
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| # invalidate | ||
| or CHCTR_DCINV,d0 | ||
| movhu d0,(a0) | ||
| movhu (a0),d0 | ||
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| #endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ | ||
| .endm |