ARM: 6459/2: sa1100: Add nanoEngine PCI support.

This patch adds nanoEngine's PCI support. Signed-off-by: Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
git-mirror · Dec 21, 2010 · b080ac8 · b080ac8
1 parent fa87672
commit b080ac8
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Showing 7 changed files with 334 additions and 4 deletions.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
@@ -1164,7 +1164,7 @@ config ISA_DMA_API
 	bool
 
 config PCI
-	bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
+	bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX || SA1100_NANOENGINE
 	help
 	  Find out whether you have a PCI motherboard. PCI is the name of a
 	  bus system, i.e. the way the CPU talks to the other stuff inside
@@ -1175,6 +1175,12 @@ config PCI_DOMAINS
 	bool
 	depends on PCI
 
+config PCI_NANOENGINE
+	bool "BSE nanoEngine PCI support"
+	depends on SA1100_NANOENGINE
+	help
+	  Enable PCI on the BSE nanoEngine board.
+
 config PCI_SYSCALL
 	def_bool PCI
 

diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
@@ -121,6 +121,8 @@ config SA1100_LART
 config SA1100_NANOENGINE
 	bool "nanoEngine"
 	select CPU_FREQ_SA1110
+	select PCI
+	select PCI_NANOENGINE
 	help
 	  Say Y here if you are using the Bright Star Engineering nanoEngine.
 	  See <http://www.brightstareng.com/arm/nanoeng.htm> for information

diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_SA1100_LART)		+= lart.o
 led-$(CONFIG_SA1100_LART)		+= leds-lart.o
 
 obj-$(CONFIG_SA1100_NANOENGINE)		+= nanoengine.o
+obj-$(CONFIG_PCI_NANOENGINE)		+= pci-nanoengine.o
 
 obj-$(CONFIG_SA1100_PLEB)		+= pleb.o
 

diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -76,4 +76,12 @@ static inline unsigned long get_clock_tick_rate(void)
 #include "SA-1101.h"
 #endif
 
+#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_PCI)
+#define PCIBIOS_MIN_IO		0
+#define PCIBIOS_MIN_MEM		0
+#define pcibios_assign_all_busses()	1
+#define HAVE_ARCH_PCI_SET_DMA_MASK	1
+#endif
+
+
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h
@@ -14,17 +14,39 @@
 #ifndef __ASM_ARCH_NANOENGINE_H
 #define __ASM_ARCH_NANOENGINE_H
 
+#include <mach/irqs.h>
+
 #define GPIO_PC_READY0	GPIO_GPIO(11) /* ready for socket 0 (active high)*/
 #define GPIO_PC_READY1	GPIO_GPIO(12) /* ready for socket 1 (active high) */
 #define GPIO_PC_CD0	GPIO_GPIO(13) /* detect for socket 0 (active low) */
 #define GPIO_PC_CD1	GPIO_GPIO(14) /* detect for socket 1 (active low) */
 #define GPIO_PC_RESET0	GPIO_GPIO(15) /* reset socket 0 */
 #define GPIO_PC_RESET1	GPIO_GPIO(16) /* reset socket 1 */
 
+#define NANOENGINE_IRQ_GPIO_PCI		IRQ_GPIO0
 #define NANOENGINE_IRQ_GPIO_PC_READY0	IRQ_GPIO11
 #define NANOENGINE_IRQ_GPIO_PC_READY1	IRQ_GPIO12
 #define NANOENGINE_IRQ_GPIO_PC_CD0	IRQ_GPIO13
 #define NANOENGINE_IRQ_GPIO_PC_CD1	IRQ_GPIO14
 
+/*
+ * nanoEngine Memory Map:
+ *
+ * 0000.0000 - 003F.0000 -   4 MB Flash
+ * C000.0000 - C1FF.FFFF -  32 MB SDRAM
+ * 1860.0000 - 186F.FFFF -   1 MB Internal PCI Memory Read/Write
+ * 18A1.0000 - 18A1.FFFF -  64 KB Internal PCI Config Space
+ * 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode
+ * 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode
+ *
+ */
+
+#define NANO_PCI_MEM_RW_PHYS		0x18600000
+#define NANO_PCI_MEM_RW_VIRT		0xf1000000
+#define NANO_PCI_MEM_RW_SIZE		SZ_1M
+#define NANO_PCI_CONFIG_SPACE_PHYS	0x18A10000
+#define NANO_PCI_CONFIG_SPACE_VIRT	0xf2000000
+#define NANO_PCI_CONFIG_SPACE_SIZE	SZ_64K
+
 #endif
 
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c
@@ -26,6 +26,7 @@
 #include <asm/mach/serial_sa1100.h>
 
 #include <mach/hardware.h>
+#include <mach/nanoengine.h>
 
 #include "generic.h"
 
@@ -74,11 +75,17 @@ static struct map_desc nanoengine_io_desc[] __initdata = {
 		.pfn		= __phys_to_pfn(0x10000000),
 		.length		= 0x00100000,
 		.type		= MT_DEVICE
+	}, {
+		/* Internal PCI Memory Read/Write */
+		.virtual	= NANO_PCI_MEM_RW_VIRT,
+		.pfn		= __phys_to_pfn(NANO_PCI_MEM_RW_PHYS),
+		.length		= NANO_PCI_MEM_RW_SIZE,
+		.type		= MT_DEVICE
 	}, {
 		/* Internal PCI Config Space */
-		.virtual	= 0xf1000000,
-		.pfn		= __phys_to_pfn(0x18A00000),
-		.length		= 0x00100000,
+		.virtual	= NANO_PCI_CONFIG_SPACE_VIRT,
+		.pfn		= __phys_to_pfn(NANO_PCI_CONFIG_SPACE_PHYS),
+		.length		= NANO_PCI_CONFIG_SPACE_SIZE,
 		.type		= MT_DEVICE
 	}
 };