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Pawel Moll
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Feb 24, 2012
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--- | ||
refs/heads/master: cca070a916fb8ba78bb1494a35ae01f20eff5a57 | ||
refs/heads/master: 059289b260826deb43601644a7ad39c2608e6861 |
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/* | ||
* ARM Ltd. Versatile Express | ||
* | ||
* CoreTile Express A15x2 (version with Test Chip 1) | ||
* Cortex-A15 MPCore (V2P-CA15) | ||
* | ||
* HBI-0237A | ||
*/ | ||
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/dts-v1/; | ||
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/ { | ||
model = "V2P-CA15"; | ||
arm,hbi = <0x237>; | ||
compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; | ||
interrupt-parent = <&gic>; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
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chosen { }; | ||
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aliases { | ||
serial0 = &v2m_serial0; | ||
serial1 = &v2m_serial1; | ||
serial2 = &v2m_serial2; | ||
serial3 = &v2m_serial3; | ||
i2c0 = &v2m_i2c_dvi; | ||
i2c1 = &v2m_i2c_pcie; | ||
}; | ||
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cpus { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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cpu@0 { | ||
device_type = "cpu"; | ||
compatible = "arm,cortex-a15"; | ||
reg = <0>; | ||
}; | ||
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cpu@1 { | ||
device_type = "cpu"; | ||
compatible = "arm,cortex-a15"; | ||
reg = <1>; | ||
}; | ||
}; | ||
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memory@80000000 { | ||
device_type = "memory"; | ||
reg = <0x80000000 0x40000000>; | ||
}; | ||
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hdlcd@2b000000 { | ||
compatible = "arm,hdlcd"; | ||
reg = <0x2b000000 0x1000>; | ||
interrupts = <0 85 4>; | ||
}; | ||
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memory-controller@2b0a0000 { | ||
compatible = "arm,pl341", "arm,primecell"; | ||
reg = <0x2b0a0000 0x1000>; | ||
}; | ||
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wdt@2b060000 { | ||
compatible = "arm,sp805", "arm,primecell"; | ||
reg = <0x2b060000 0x1000>; | ||
interrupts = <98>; | ||
}; | ||
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gic: interrupt-controller@2c001000 { | ||
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; | ||
#interrupt-cells = <3>; | ||
#address-cells = <0>; | ||
interrupt-controller; | ||
reg = <0x2c001000 0x1000>, | ||
<0x2c002000 0x100>; | ||
}; | ||
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memory-controller@7ffd0000 { | ||
compatible = "arm,pl354", "arm,primecell"; | ||
reg = <0x7ffd0000 0x1000>; | ||
interrupts = <0 86 4>, | ||
<0 87 4>; | ||
}; | ||
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dma@7ffb0000 { | ||
compatible = "arm,pl330", "arm,primecell"; | ||
reg = <0x7ffb0000 0x1000>; | ||
interrupts = <0 92 4>, | ||
<0 88 4>, | ||
<0 89 4>, | ||
<0 90 4>, | ||
<0 91 4>; | ||
}; | ||
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pmu { | ||
compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; | ||
interrupts = <0 68 4>, | ||
<0 69 4>; | ||
}; | ||
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motherboard { | ||
ranges = <0 0 0x08000000 0x04000000>, | ||
<1 0 0x14000000 0x04000000>, | ||
<2 0 0x18000000 0x04000000>, | ||
<3 0 0x1c000000 0x04000000>, | ||
<4 0 0x0c000000 0x04000000>, | ||
<5 0 0x10000000 0x04000000>; | ||
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interrupt-map-mask = <0 0 63>; | ||
interrupt-map = <0 0 0 &gic 0 0 4>, | ||
<0 0 1 &gic 0 1 4>, | ||
<0 0 2 &gic 0 2 4>, | ||
<0 0 3 &gic 0 3 4>, | ||
<0 0 4 &gic 0 4 4>, | ||
<0 0 5 &gic 0 5 4>, | ||
<0 0 6 &gic 0 6 4>, | ||
<0 0 7 &gic 0 7 4>, | ||
<0 0 8 &gic 0 8 4>, | ||
<0 0 9 &gic 0 9 4>, | ||
<0 0 10 &gic 0 10 4>, | ||
<0 0 11 &gic 0 11 4>, | ||
<0 0 12 &gic 0 12 4>, | ||
<0 0 13 &gic 0 13 4>, | ||
<0 0 14 &gic 0 14 4>, | ||
<0 0 15 &gic 0 15 4>, | ||
<0 0 16 &gic 0 16 4>, | ||
<0 0 17 &gic 0 17 4>, | ||
<0 0 18 &gic 0 18 4>, | ||
<0 0 19 &gic 0 19 4>, | ||
<0 0 20 &gic 0 20 4>, | ||
<0 0 21 &gic 0 21 4>, | ||
<0 0 22 &gic 0 22 4>, | ||
<0 0 23 &gic 0 23 4>, | ||
<0 0 24 &gic 0 24 4>, | ||
<0 0 25 &gic 0 25 4>, | ||
<0 0 26 &gic 0 26 4>, | ||
<0 0 27 &gic 0 27 4>, | ||
<0 0 28 &gic 0 28 4>, | ||
<0 0 29 &gic 0 29 4>, | ||
<0 0 30 &gic 0 30 4>, | ||
<0 0 31 &gic 0 31 4>, | ||
<0 0 32 &gic 0 32 4>, | ||
<0 0 33 &gic 0 33 4>, | ||
<0 0 34 &gic 0 34 4>, | ||
<0 0 35 &gic 0 35 4>, | ||
<0 0 36 &gic 0 36 4>, | ||
<0 0 37 &gic 0 37 4>, | ||
<0 0 38 &gic 0 38 4>, | ||
<0 0 39 &gic 0 39 4>, | ||
<0 0 40 &gic 0 40 4>, | ||
<0 0 41 &gic 0 41 4>, | ||
<0 0 42 &gic 0 42 4>; | ||
}; | ||
}; | ||
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/include/ "vexpress-v2m-rs1.dtsi" |
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#define IRQ_LOCALTIMER 29 | ||
#define IRQ_LOCALWDOG 30 | ||
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#define NR_IRQS 128 | ||
#define NR_IRQS 256 |