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Merge tag 'sunxi-dt-for-3.10-2' of git://github.com/mripard/linux int…
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…o next/dt

From Maxime Ripard <maxime.ripard@free-electrons.com>:

ARM: sunxi: dt additions for 3.10, take 2

  - Rename the clock compatible introduced in the first pull request for 3.10
  - Complete the UART support for A13 and A10
  - Adds clock gates support

* tag 'sunxi-dt-for-3.10-2' of git://github.com/mripard/linux:
  arm: sunxi: Add clock to pinctrl node
  arm: sunxi: use the right clock phandles for UARTs
  arm: sunxi: Add clock definitions for AXI, AHB, APB0, APB1 gates
  ARM: sunxi: cubieboard: Add UART muxing
  ARM: sunxi: hackberry: Add UART muxing
  ARM: sunxi: dt: Add A10 UARTs to the dtsi.
  ARM: sunxi: dt: Add uart3 dt node
  ARM: sunxi: dt: Move uart0 to sun4i-a10.dtsi
  ARM: sunxi: Rename uart nodes to serial
  ARM: sunxi: dt: Use clocks property instead of clock-frequency for the UARTs
  arm: sunxi: rename clock compatible strings

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann committed Apr 8, 2013
2 parents e52ec42 + 36386d6 commit b26cd30
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Showing 6 changed files with 134 additions and 23 deletions.
8 changes: 3 additions & 5 deletions arch/arm/boot/dts/sun4i-a10-cubieboard.dts
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Expand Up @@ -36,11 +36,9 @@
};
};

uart0: uart@01c28000 {
status = "okay";
};

uart1: uart@01c28400 {
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
};
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4 changes: 3 additions & 1 deletion arch/arm/boot/dts/sun4i-a10-hackberry.dts
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Expand Up @@ -23,7 +23,9 @@
};

soc {
uart0: uart@01c28000 {
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
};
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61 changes: 61 additions & 0 deletions arch/arm/boot/dts/sun4i-a10.dtsi
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Expand Up @@ -21,6 +21,7 @@
pio: pinctrl@01c20800 {
compatible = "allwinner,sun4i-a10-pinctrl";
reg = <0x01c20800 0x400>;
clocks = <&apb0_gates 5>;
gpio-controller;
#address-cells = <1>;
#size-cells = <0>;
Expand All @@ -47,5 +48,65 @@
allwinner,pull = <0>;
};
};

uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 16>;
status = "disabled";
};

uart2: serial@01c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <3>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 18>;
status = "disabled";
};

uart4: serial@01c29000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29000 0x400>;
interrupts = <17>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 20>;
status = "disabled";
};

uart5: serial@01c29400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29400 0x400>;
interrupts = <18>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 21>;
status = "disabled";
};

uart6: serial@01c29800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29800 0x400>;
interrupts = <19>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 22>;
status = "disabled";
};

uart7: serial@01c29c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29c00 0x400>;
interrupts = <20>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 23>;
status = "disabled";
};
};
};
2 changes: 1 addition & 1 deletion arch/arm/boot/dts/sun5i-a13-olinuxino.dts
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Expand Up @@ -32,7 +32,7 @@
};
};

uart1: uart@01c28400 {
uart1: serial@01c28400 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>;
status = "okay";
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1 change: 1 addition & 0 deletions arch/arm/boot/dts/sun5i-a13.dtsi
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Expand Up @@ -22,6 +22,7 @@
pio: pinctrl@01c20800 {
compatible = "allwinner,sun5i-a13-pinctrl";
reg = <0x01c20800 0x400>;
clocks = <&apb0_gates 5>;
gpio-controller;
#address-cells = <1>;
#size-cells = <0>;
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81 changes: 65 additions & 16 deletions arch/arm/boot/dts/sunxi.dtsi
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Expand Up @@ -47,7 +47,7 @@

osc24M: osc24M@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-osc-clk";
compatible = "allwinner,sun4i-osc-clk";
reg = <0x01c20050 0x4>;
clocks = <&osc24M_fixed>;
};
Expand All @@ -60,54 +60,103 @@

pll1: pll1@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-pll1-clk";
compatible = "allwinner,sun4i-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
};

/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-cpu-clk";
compatible = "allwinner,sun4i-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
};

axi: axi@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-axi-clk";
compatible = "allwinner,sun4i-axi-clk";
reg = <0x01c20054 0x4>;
clocks = <&cpu>;
};

axi_gates: axi_gates@01c2005c {
#clock-cells = <1>;
compatible = "allwinner,sun4i-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
clock-output-names = "axi_dram";
};

ahb: ahb@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-ahb-clk";
compatible = "allwinner,sun4i-ahb-clk";
reg = <0x01c20054 0x4>;
clocks = <&axi>;
};

ahb_gates: ahb_gates@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
"ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
"ahb_de_fe1", "ahb_mp", "ahb_mali400";
};

apb0: apb0@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-apb0-clk";
compatible = "allwinner,sun4i-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb>;
};

apb0_gates: apb0_gates@01c20068 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
clock-output-names = "apb0_codec", "apb0_spdif",
"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
"apb0_ir1", "apb0_keypad";
};

/* dummy is pll62 */
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-apb1-mux-clk";
compatible = "allwinner,sun4i-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&dummy>, <&osc32k>;
};

apb1: apb1@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sunxi-apb1-clk";
compatible = "allwinner,sun4i-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&apb1_mux>;
};

apb1_gates: apb1_gates@01c2006c {
#clock-cells = <1>;
compatible = "allwinner,sun4i-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_can", "apb1_scr",
"apb1_ps20", "apb1_ps21", "apb1_uart0",
"apb1_uart1", "apb1_uart2", "apb1_uart3",
"apb1_uart4", "apb1_uart5", "apb1_uart6",
"apb1_uart7";
};
};

soc {
Expand Down Expand Up @@ -136,23 +185,23 @@
#interrupt-cells = <1>;
};

uart0: uart@01c28000 {
uart1: serial@01c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <1>;
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&apb1_gates 17>;
status = "disabled";
};

uart1: uart@01c28400 {
uart3: serial@01c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg = <0x01c28c00 0x400>;
interrupts = <4>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&apb1_gates 19>;
status = "disabled";
};
};
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