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Attention linux-next maintainer, you will hit a merge conflict between
this merge and the mips tree, the resolution is to preserve the removal
of uses of nvram_geenv() and nvram_parse_macaddr() from the net-next
side.

Hauke Mehrtens says:

====================
These patches are adding support for the Ethernet core found in the
BCM4705/BCM4785 SoC.

This is based on current master of davem/net-next.git.

v4:
 * move setting of DMA_RWCTRL_ONE_DMA

v3:
 * combined first two patches into one patch

v2:
 * use of struct sprom in ssb_gige_get_macaddr() instead of accessing
   the nvram directly
 * add return value to ssb_gige_get_macaddr()
 * try to read the mac address from ssb core before accessing the own
   registers.
 * fix two checkpatch warnings
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller committed Feb 8, 2013
2 parents 241448c + 7e6c63f commit b285109
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Showing 4 changed files with 148 additions and 24 deletions.
143 changes: 131 additions & 12 deletions drivers/net/ethernet/broadcom/tg3.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,7 @@
#include <linux/prefetch.h>
#include <linux/dma-mapping.h>
#include <linux/firmware.h>
#include <linux/ssb/ssb_driver_gige.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>

Expand Down Expand Up @@ -263,6 +264,7 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
TG3_DRV_DATA_FLAG_5705_10_100},
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
Expand Down Expand Up @@ -573,7 +575,9 @@ static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
{
tp->write32_mbox(tp, off, val);
if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
(!tg3_flag(tp, MBOX_WRITE_REORDER) &&
!tg3_flag(tp, ICH_WORKAROUND)))
tp->read32_mbox(tp, off);
}

Expand All @@ -583,7 +587,8 @@ static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
writel(val, mbox);
if (tg3_flag(tp, TXD_MBOX_HWBUG))
writel(val, mbox);
if (tg3_flag(tp, MBOX_WRITE_REORDER))
if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
tg3_flag(tp, FLUSH_POSTED_WRITES))
readl(mbox);
}

Expand Down Expand Up @@ -1091,7 +1096,8 @@ static void tg3_switch_clocks(struct tg3 *tp)

#define PHY_BUSY_LOOPS 5000

static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
u32 *val)
{
u32 frame_val;
unsigned int loops;
Expand All @@ -1107,7 +1113,7 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)

*val = 0x0;

frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
MI_COM_PHY_ADDR_MASK);
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
MI_COM_REG_ADDR_MASK);
Expand Down Expand Up @@ -1144,7 +1150,13 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
return ret;
}

static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
{
return __tg3_readphy(tp, tp->phy_addr, reg, val);
}

static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
u32 val)
{
u32 frame_val;
unsigned int loops;
Expand All @@ -1162,7 +1174,7 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)

tg3_ape_lock(tp, tp->phy_ape_lock);

frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
MI_COM_PHY_ADDR_MASK);
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
MI_COM_REG_ADDR_MASK);
Expand Down Expand Up @@ -1197,6 +1209,11 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
return ret;
}

static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
{
return __tg3_writephy(tp, tp->phy_addr, reg, val);
}

static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
{
int err;
Expand Down Expand Up @@ -1781,6 +1798,11 @@ static int tg3_poll_fw(struct tg3 *tp)
int i;
u32 val;

if (tg3_flag(tp, IS_SSB_CORE)) {
/* We don't use firmware. */
return 0;
}

if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
/* Wait up to 20ms for init done. */
for (i = 0; i < 200; i++) {
Expand Down Expand Up @@ -3453,6 +3475,13 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
udelay(10);
} else {
/*
* There is only an Rx CPU for the 5750 derivative in the
* BCM4785.
*/
if (tg3_flag(tp, IS_SSB_CORE))
return 0;

for (i = 0; i < 10000; i++) {
tw32(offset + CPU_STATE, 0xffffffff);
tw32(offset + CPU_MODE, CPU_MODE_HALT);
Expand Down Expand Up @@ -3920,8 +3949,9 @@ static int tg3_power_down_prepare(struct tg3 *tp)
tg3_frob_aux_power(tp, true);

/* Workaround for unstable PLL clock */
if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
(GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
if ((!tg3_flag(tp, IS_SSB_CORE)) &&
((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
(GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
u32 val = tr32(0x7d00);

val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
Expand Down Expand Up @@ -4442,6 +4472,15 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
tg3_phy_copper_begin(tp);

if (tg3_flag(tp, ROBOSWITCH)) {
current_link_up = 1;
/* FIXME: when BCM5325 switch is used use 100 MBit/s */
current_speed = SPEED_1000;
current_duplex = DUPLEX_FULL;
tp->link_config.active_speed = current_speed;
tp->link_config.active_duplex = current_duplex;
}

tg3_readphy(tp, MII_BMSR, &bmsr);
if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
Expand All @@ -4460,6 +4499,26 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
else
tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;

/* In order for the 5750 core in BCM4785 chip to work properly
* in RGMII mode, the Led Control Register must be set up.
*/
if (tg3_flag(tp, RGMII_MODE)) {
u32 led_ctrl = tr32(MAC_LED_CTRL);
led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);

if (tp->link_config.active_speed == SPEED_10)
led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
else if (tp->link_config.active_speed == SPEED_100)
led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
LED_CTRL_100MBPS_ON);
else if (tp->link_config.active_speed == SPEED_1000)
led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
LED_CTRL_1000MBPS_ON);

tw32(MAC_LED_CTRL, led_ctrl);
udelay(40);
}

tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
if (tp->link_config.active_duplex == DUPLEX_HALF)
tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
Expand Down Expand Up @@ -8437,6 +8496,16 @@ static int tg3_chip_reset(struct tg3 *tp)
tw32(0x5000, 0x400);
}

if (tg3_flag(tp, IS_SSB_CORE)) {
/*
* BCM4785: In order to avoid repercussions from using
* potentially defective internal ROM, stop the Rx RISC CPU,
* which is not required.
*/
tg3_stop_fw(tp);
tg3_halt_cpu(tp, RX_CPU_BASE);
}

tw32(GRC_MODE, tp->grc_mode);

if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
Expand Down Expand Up @@ -10095,6 +10164,11 @@ static void tg3_timer(unsigned long __opaque)
tg3_flag(tp, 57765_CLASS))
tg3_chk_missed_msi(tp);

if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
/* BCM4785: Flush posted writes from GbE to host memory. */
tr32(HOSTCC_MODE);
}

if (!tg3_flag(tp, TAGGED_STATUS)) {
/* All of this garbage is because when using non-tagged
* IRQ status the mailbox/status_block protocol the chip
Expand Down Expand Up @@ -12969,7 +13043,8 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
return -EAGAIN;

spin_lock_bh(&tp->lock);
err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
err = __tg3_readphy(tp, data->phy_id & 0x1f,
data->reg_num & 0x1f, &mii_regval);
spin_unlock_bh(&tp->lock);

data->val_out = mii_regval;
Expand All @@ -12985,7 +13060,8 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
return -EAGAIN;

spin_lock_bh(&tp->lock);
err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
err = __tg3_writephy(tp, data->phy_id & 0x1f,
data->reg_num & 0x1f, data->val_in);
spin_unlock_bh(&tp->lock);

return err;
Expand Down Expand Up @@ -13865,6 +13941,14 @@ static void tg3_get_5720_nvram_info(struct tg3 *tp)
/* Chips other than 5700/5701 use the NVRAM for fetching info. */
static void tg3_nvram_init(struct tg3 *tp)
{
if (tg3_flag(tp, IS_SSB_CORE)) {
/* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
tg3_flag_clear(tp, NVRAM);
tg3_flag_clear(tp, NVRAM_BUFFERED);
tg3_flag_set(tp, NO_NVRAM);
return;
}

tw32_f(GRC_EEPROM_ADDR,
(EEPROM_ADDR_FSM_RESET |
(EEPROM_DEFAULT_CLOCK_PERIOD <<
Expand Down Expand Up @@ -14391,10 +14475,19 @@ static int tg3_phy_probe(struct tg3 *tp)
* subsys device table.
*/
p = tg3_lookup_by_subsys(tp);
if (!p)
if (p) {
tp->phy_id = p->phy_id;
} else if (!tg3_flag(tp, IS_SSB_CORE)) {
/* For now we saw the IDs 0xbc050cd0,
* 0xbc050f80 and 0xbc050c30 on devices
* connected to an BCM4785 and there are
* probably more. Just assume that the phy is
* supported when it is connected to a SSB core
* for now.
*/
return -ENODEV;
}

tp->phy_id = p->phy_id;
if (!tp->phy_id ||
tp->phy_id == TG3_PHY_ID_BCM8002)
tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
Expand Down Expand Up @@ -15470,6 +15563,11 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
TG3_CPMU_STATUS_FSHFT_5719;
}

if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
tp->write32_tx_mbox = tg3_write_flush_reg32;
tp->write32_rx_mbox = tg3_write_flush_reg32;
}

/* Get eeprom hw config before calling tg3_set_power_state().
* In particular, the TG3_FLAG_IS_NIC flag must be
* determined before calling tg3_set_power_state() so that
Expand Down Expand Up @@ -15806,12 +15904,19 @@ static int tg3_get_device_address(struct tg3 *tp)
struct net_device *dev = tp->dev;
u32 hi, lo, mac_offset;
int addr_ok = 0;
int err;

#ifdef CONFIG_SPARC
if (!tg3_get_macaddr_sparc(tp))
return 0;
#endif

if (tg3_flag(tp, IS_SSB_CORE)) {
err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
return 0;
}

mac_offset = 0x7c;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
tg3_flag(tp, 5780_CLASS)) {
Expand Down Expand Up @@ -16171,6 +16276,8 @@ static int tg3_test_dma(struct tg3 *tp)
tp->dma_rwctrl |= 0x001b000f;
}
}
if (tg3_flag(tp, ONE_DMA_AT_ONCE))
tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;

if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
Expand Down Expand Up @@ -16516,6 +16623,18 @@ static int tg3_init_one(struct pci_dev *pdev,
else
tp->msg_enable = TG3_DEF_MSG_ENABLE;

if (pdev_is_ssb_gige_core(pdev)) {
tg3_flag_set(tp, IS_SSB_CORE);
if (ssb_gige_must_flush_posted_writes(pdev))
tg3_flag_set(tp, FLUSH_POSTED_WRITES);
if (ssb_gige_one_dma_at_once(pdev))
tg3_flag_set(tp, ONE_DMA_AT_ONCE);
if (ssb_gige_have_roboswitch(pdev))
tg3_flag_set(tp, ROBOSWITCH);
if (ssb_gige_is_rgmii(pdev))
tg3_flag_set(tp, RGMII_MODE);
}

/* The word/byte swap controls here control register access byte
* swapping. DMA data byte swapping is controlled in the GRC_MODE
* setting below.
Expand Down
5 changes: 5 additions & 0 deletions drivers/net/ethernet/broadcom/tg3.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3056,6 +3056,11 @@ enum TG3_FLAGS {
TG3_FLAG_57765_PLUS,
TG3_FLAG_57765_CLASS,
TG3_FLAG_5717_PLUS,
TG3_FLAG_IS_SSB_CORE,
TG3_FLAG_FLUSH_POSTED_WRITES,
TG3_FLAG_ROBOSWITCH,
TG3_FLAG_ONE_DMA_AT_ONCE,
TG3_FLAG_RGMII_MODE,

/* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
Expand Down
1 change: 1 addition & 0 deletions include/linux/pci_ids.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2127,6 +2127,7 @@
#define PCI_DEVICE_ID_TIGON3_5754M 0x1672
#define PCI_DEVICE_ID_TIGON3_5755M 0x1673
#define PCI_DEVICE_ID_TIGON3_5756 0x1674
#define PCI_DEVICE_ID_TIGON3_5750 0x1676
#define PCI_DEVICE_ID_TIGON3_5751 0x1677
#define PCI_DEVICE_ID_TIGON3_5715 0x1678
#define PCI_DEVICE_ID_TIGON3_5715S 0x1679
Expand Down
23 changes: 11 additions & 12 deletions include/linux/ssb/ssb_driver_gige.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -97,21 +97,16 @@ static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
return 0;
}

#ifdef CONFIG_BCM47XX
#include <asm/mach-bcm47xx/nvram.h>
/* Get the device MAC address */
static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
{
char buf[20];
if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
return;
nvram_parse_macaddr(buf, macaddr);
}
#else
static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
{
struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
if (!dev)
return -ENODEV;

memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
return 0;
}
#endif

extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
struct pci_dev *pdev);
Expand Down Expand Up @@ -175,6 +170,10 @@ static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
{
return 0;
}
static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
{
return -ENODEV;
}

#endif /* CONFIG_SSB_DRIVER_GIGE */
#endif /* LINUX_SSB_DRIVER_GIGE_H_ */

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