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[ARM] 4145/2: AT91: Add support for AT91SAM9263 processor
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Add support for the Atmel AT91SAM9263 processor.  It is similar to the
AT91SAM9260 but with more integrated peripherals, 5 GPIO banks, etc.

Original patch from Nicolas Ferre.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Andrew Victor authored and Russell King committed Feb 8, 2007
1 parent d0760b3 commit b2c6561
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Showing 15 changed files with 1,425 additions and 5 deletions.
3 changes: 3 additions & 0 deletions arch/arm/mach-at91/Kconfig
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Expand Up @@ -14,6 +14,9 @@ config ARCH_AT91SAM9260
config ARCH_AT91SAM9261
bool "AT91SAM9261"

config ARCH_AT91SAM9263
bool "AT91SAM9263"

endchoice

# ----------------------------------------------------------
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1 change: 1 addition & 0 deletions arch/arm/mach-at91/Makefile
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Expand Up @@ -13,6 +13,7 @@ obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o

# AT91RM9200 board-specific support
obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
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313 changes: 313 additions & 0 deletions arch/arm/mach-at91/at91sam9263.c
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@@ -0,0 +1,313 @@
/*
* arch/arm/mach-at91/at91sam9263.c
*
* Copyright (C) 2007 Atmel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/

#include <linux/module.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>

#include "generic.h"
#include "clock.h"

static struct map_desc at91sam9263_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE,
.pfn = __phys_to_pfn(AT91SAM9263_SRAM0_BASE),
.length = AT91SAM9263_SRAM0_SIZE,
.type = MT_DEVICE,
}, {
.virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE - AT91SAM9263_SRAM1_SIZE,
.pfn = __phys_to_pfn(AT91SAM9263_SRAM1_BASE),
.length = AT91SAM9263_SRAM1_SIZE,
.type = MT_DEVICE,
},
};

/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */

/*
* The peripheral clocks.
*/
static struct clk pioA_clk = {
.name = "pioA_clk",
.pmc_mask = 1 << AT91SAM9263_ID_PIOA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
.name = "pioB_clk",
.pmc_mask = 1 << AT91SAM9263_ID_PIOB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioCDE_clk = {
.name = "pioCDE_clk",
.pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
.name = "usart0_clk",
.pmc_mask = 1 << AT91SAM9263_ID_US0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
.name = "usart1_clk",
.pmc_mask = 1 << AT91SAM9263_ID_US1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
.name = "usart2_clk",
.pmc_mask = 1 << AT91SAM9263_ID_US2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
.name = "mci0_clk",
.pmc_mask = 1 << AT91SAM9263_ID_MCI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
.name = "mci1_clk",
.pmc_mask = 1 << AT91SAM9263_ID_MCI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
.name = "twi_clk",
.pmc_mask = 1 << AT91SAM9263_ID_TWI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
.name = "spi0_clk",
.pmc_mask = 1 << AT91SAM9263_ID_SPI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
.name = "spi1_clk",
.pmc_mask = 1 << AT91SAM9263_ID_SPI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tcb_clk = {
.name = "tcb_clk",
.pmc_mask = 1 << AT91SAM9263_ID_TCB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ether_clk = {
.name = "ether_clk",
.pmc_mask = 1 << AT91SAM9263_ID_EMAC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk udc_clk = {
.name = "udc_clk",
.pmc_mask = 1 << AT91SAM9263_ID_UDP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
.name = "isi_clk",
.pmc_mask = 1 << AT91SAM9263_ID_ISI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
.name = "lcdc_clk",
.pmc_mask = 1 << AT91SAM9263_ID_ISI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
.name = "ohci_clk",
.pmc_mask = 1 << AT91SAM9263_ID_UHP,
.type = CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
&pioA_clk,
&pioB_clk,
&pioCDE_clk,
&usart0_clk,
&usart1_clk,
&usart2_clk,
&mmc0_clk,
&mmc1_clk,
// can
&twi_clk,
&spi0_clk,
&spi1_clk,
// ssc0 .. ssc1
// ac97
&tcb_clk,
// pwmc
&ether_clk,
// 2dge
&udc_clk,
&isi_clk,
&lcdc_clk,
// dma
&ohci_clk,
// irq0 .. irq1
};

/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 1,
};
static struct clk pck2 = {
.name = "pck2",
.pmc_mask = AT91_PMC_PCK2,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 2,
};
static struct clk pck3 = {
.name = "pck3",
.pmc_mask = AT91_PMC_PCK3,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 3,
};

static void __init at91sam9263_register_clocks(void)
{
int i;

for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);

clk_register(&pck0);
clk_register(&pck1);
clk_register(&pck2);
clk_register(&pck3);
}

/* --------------------------------------------------------------------
* GPIO
* -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9263_gpio[] = {
{
.id = AT91SAM9263_ID_PIOA,
.offset = AT91_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9263_ID_PIOB,
.offset = AT91_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.offset = AT91_PIOC,
.clock = &pioCDE_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.offset = AT91_PIOD,
.clock = &pioCDE_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.offset = AT91_PIOE,
.clock = &pioCDE_clk,
}
};

static void at91sam9263_reset(void)
{
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}


/* --------------------------------------------------------------------
* AT91SAM9263 processor initialization
* -------------------------------------------------------------------- */

void __init at91sam9263_initialize(unsigned long main_clock)
{
/* Map peripherals */
iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));

at91_arch_reset = at91sam9263_reset;
at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);

/* Init clock subsystem */
at91_clock_init(main_clock);

/* Register the processor-specific clocks */
at91sam9263_register_clocks();

/* Register GPIO subsystem */
at91_gpio_init(at91sam9263_gpio, 5);
}

/* --------------------------------------------------------------------
* Interrupt initialization
* -------------------------------------------------------------------- */

/*
* The default interrupt priority levels (0 = lowest, 7 = highest).
*/
static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
7, /* Advanced Interrupt Controller (FIQ) */
7, /* System Peripherals */
0, /* Parallel IO Controller A */
0, /* Parallel IO Controller B */
0, /* Parallel IO Controller C, D and E */
0,
0,
6, /* USART 0 */
6, /* USART 1 */
6, /* USART 2 */
0, /* Multimedia Card Interface 0 */
0, /* Multimedia Card Interface 1 */
4, /* CAN */
0, /* Two-Wire Interface */
6, /* Serial Peripheral Interface 0 */
6, /* Serial Peripheral Interface 1 */
5, /* Serial Synchronous Controller 0 */
5, /* Serial Synchronous Controller 1 */
6, /* AC97 Controller */
0, /* Timer Counter 0, 1 and 2 */
0, /* Pulse Width Modulation Controller */
3, /* Ethernet */
0,
0, /* 2D Graphic Engine */
3, /* USB Device Port */
0, /* Image Sensor Interface */
3, /* LDC Controller */
0, /* DMA Controller */
0,
3, /* USB Host port */
0, /* Advanced Interrupt Controller (IRQ0) */
0, /* Advanced Interrupt Controller (IRQ1) */
};

void __init at91sam9263_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
if (!priority)
priority = at91sam9263_default_irq_priority;

/* Initialize the AIC interrupt controller */
at91_aic_init(priority);

/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}
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