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Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/a…
…rm-soc Pull device tree conversions for arm-soc, part 1, from Olof Johansson: "The spear3xx, lpc32xx, shmobile and mmp platforms are joining the game of booting using device trees, which is a great step forward for them. at91 and spear have pretty much completed this process with a huge amount of work being put into at91. The other platforms are continuing the process. We finally start to see the payback on this investment, as new machines are getting supported purely by adding a .dts source file that can be completely independent of the kernel source." Fix up trivial conflict in arch/arm/Kconfig * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits) ARM: at91: Add ADC driver to at91sam9260/at91sam9g20 dtsi files arm/dts: omap4-panda: Add LEDs support arm/dts: omap4-sdp: Add LEDs support arm/dts: twl4030: Add twl4030-gpio node OMAP4: devices: Do not create mcpdm device if the dtb has been provided OMAP4: devices: Do not create dmic device if the dtb has been provided Documentation: update docs for mmp dt ARM: dts: refresh dts file for arch mmp ARM: mmp: support pxa910 with device tree ARM: mmp: support mmp2 with device tree gpio: pxa: parse gpio from DTS file ARM: mmp: support DT in timer ARM: mmp: support DT in irq ARM: mmp: append CONFIG_MACH_MMP2_DT ARM: mmp: fix build issue on mmp with device tree ARM: ux500: Enable PRCMU Timer 4 (clocksource) for Device Tree ARM: ux500: Disable SMSC911x platform code registration when DT is enabled ARM: ux500: Fork cpu-db8500 platform_devs for sequential DT enablement ARM: ux500: Do not attempt to register non-existent i2c devices on Snowball ARM: SPEAr3xx: Correct keyboard data passed from DT ...
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,38 @@ | ||
| * NXP LPC32xx Main Interrupt Controller | ||
| (MIC, including SIC1 and SIC2 secondary controllers) | ||
|
|
||
| Required properties: | ||
| - compatible: Should be "nxp,lpc3220-mic" | ||
| - interrupt-controller: Identifies the node as an interrupt controller. | ||
| - interrupt-parent: Empty for the interrupt controller itself | ||
| - #interrupt-cells: The number of cells to define the interrupts. Should be 2. | ||
| The first cell is the IRQ number | ||
| The second cell is used to specify mode: | ||
| 1 = low-to-high edge triggered | ||
| 2 = high-to-low edge triggered | ||
| 4 = active high level-sensitive | ||
| 8 = active low level-sensitive | ||
| Default for internal sources should be set to 4 (active high). | ||
| - reg: Should contain MIC registers location and length | ||
|
|
||
| Examples: | ||
| /* | ||
| * MIC | ||
| */ | ||
| mic: interrupt-controller@40008000 { | ||
| compatible = "nxp,lpc3220-mic"; | ||
| interrupt-controller; | ||
| interrupt-parent; | ||
| #interrupt-cells = <2>; | ||
| reg = <0x40008000 0xC000>; | ||
| }; | ||
|
|
||
| /* | ||
| * ADC | ||
| */ | ||
| adc@40048000 { | ||
| compatible = "nxp,lpc3220-adc"; | ||
| reg = <0x40048000 0x1000>; | ||
| interrupt-parent = <&mic>; | ||
| interrupts = <39 4>; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,8 @@ | ||
| NXP LPC32xx Platforms Device Tree Bindings | ||
| ------------------------------------------ | ||
|
|
||
| Boards with the NXP LPC32xx SoC shall have the following properties: | ||
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| Required root node property: | ||
|
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| compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250" |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,40 @@ | ||
| * Marvell MMP Interrupt controller | ||
|
|
||
| Required properties: | ||
| - compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or | ||
| "mrvl,mmp2-mux-intc" | ||
| - reg : Address and length of the register set of the interrupt controller. | ||
| If the interrupt controller is intc, address and length means the range | ||
| of the whold interrupt controller. If the interrupt controller is mux-intc, | ||
| address and length means one register. Since address of mux-intc is in the | ||
| range of intc. mux-intc is secondary interrupt controller. | ||
| - reg-names : Name of the register set of the interrupt controller. It's | ||
| only required in mux-intc interrupt controller. | ||
| - interrupts : Should be the port interrupt shared by mux interrupts. It's | ||
| only required in mux-intc interrupt controller. | ||
| - interrupt-controller : Identifies the node as an interrupt controller. | ||
| - #interrupt-cells : Specifies the number of cells needed to encode an | ||
| interrupt source. | ||
| - mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt | ||
| controller. | ||
| - mrvl,clr-mfp-irq : Specifies the interrupt that needs to clear MFP edge | ||
| detection first. | ||
|
|
||
| Example: | ||
| intc: interrupt-controller@d4282000 { | ||
| compatible = "mrvl,mmp2-intc"; | ||
| interrupt-controller; | ||
| #interrupt-cells = <1>; | ||
| reg = <0xd4282000 0x1000>; | ||
| mrvl,intc-nr-irqs = <64>; | ||
| }; | ||
|
|
||
| intcmux4@d4282150 { | ||
| compatible = "mrvl,mmp2-mux-intc"; | ||
| interrupts = <4>; | ||
| interrupt-controller; | ||
| #interrupt-cells = <1>; | ||
| reg = <0x150 0x4>, <0x168 0x4>; | ||
| reg-names = "mux status", "mux mask"; | ||
| mrvl,intc-nr-irqs = <2>; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,13 @@ | ||
| * Marvell MMP Timer controller | ||
|
|
||
| Required properties: | ||
| - compatible : Should be "mrvl,mmp-timer". | ||
| - reg : Address and length of the register set of timer controller. | ||
| - interrupts : Should be the interrupt number. | ||
|
|
||
| Example: | ||
| timer0: timer@d4014000 { | ||
| compatible = "mrvl,mmp-timer"; | ||
| reg = <0xd4014000 0x100>; | ||
| interrupts = <13>; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,31 @@ | ||
| Nomadik GPIO controller | ||
|
|
||
| Required properties: | ||
| - compatible : Should be "st,nomadik-gpio". | ||
| - reg : Physical base address and length of the controller's registers. | ||
| - interrupts : The interrupt outputs from the controller. | ||
| - #gpio-cells : Should be two: | ||
| The first cell is the pin number. | ||
| The second cell is used to specify optional parameters: | ||
| - bits[3:0] trigger type and level flags: | ||
| 1 = low-to-high edge triggered. | ||
| 2 = high-to-low edge triggered. | ||
| 4 = active high level-sensitive. | ||
| 8 = active low level-sensitive. | ||
| - gpio-controller : Marks the device node as a GPIO controller. | ||
| - interrupt-controller : Marks the device node as an interrupt controller. | ||
| - gpio-bank : Specifies which bank a controller owns. | ||
| - st,supports-sleepmode : Specifies whether controller can sleep or not | ||
|
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| Example: | ||
|
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||
| gpio1: gpio@8012e080 { | ||
| compatible = "st,nomadik-gpio"; | ||
| reg = <0x8012e080 0x80>; | ||
| interrupts = <0 120 0x4>; | ||
| #gpio-cells = <2>; | ||
| gpio-controller; | ||
| interrupt-controller; | ||
| supports-sleepmode; | ||
| gpio-bank = <1>; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,36 @@ | ||
| * NXP PNX I2C Controller | ||
|
|
||
| Required properties: | ||
|
|
||
| - reg: Offset and length of the register set for the device | ||
| - compatible: should be "nxp,pnx-i2c" | ||
| - interrupts: configure one interrupt line | ||
| - #address-cells: always 1 (for i2c addresses) | ||
| - #size-cells: always 0 | ||
| - interrupt-parent: the phandle for the interrupt controller that | ||
| services interrupts for this device. | ||
|
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||
| Optional properties: | ||
|
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||
| - clock-frequency: desired I2C bus clock frequency in Hz, Default: 100000 Hz | ||
|
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||
| Examples: | ||
|
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| i2c1: i2c@400a0000 { | ||
| compatible = "nxp,pnx-i2c"; | ||
| reg = <0x400a0000 0x100>; | ||
| interrupt-parent = <&mic>; | ||
| interrupts = <51 0>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| }; | ||
|
|
||
| i2c2: i2c@400a8000 { | ||
| compatible = "nxp,pnx-i2c"; | ||
| reg = <0x400a8000 0x100>; | ||
| interrupt-parent = <&mic>; | ||
| interrupts = <50 0>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| clock-frequency = <100000>; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,24 @@ | ||
| * NXP LPC32xx SoC Ethernet Controller | ||
|
|
||
| Required properties: | ||
| - compatible: Should be "nxp,lpc-eth" | ||
| - reg: Address and length of the register set for the device | ||
| - interrupts: Should contain ethernet controller interrupt | ||
|
|
||
| Optional properties: | ||
| - phy-mode: String, operation mode of the PHY interface. | ||
| Supported values are: "mii", "rmii" (default) | ||
| - use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering | ||
| - local-mac-address : 6 bytes, mac address | ||
|
|
||
| Example: | ||
|
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| mac: ethernet@31060000 { | ||
| compatible = "nxp,lpc-eth"; | ||
| reg = <0x31060000 0x1000>; | ||
| interrupt-parent = <&mic>; | ||
| interrupts = <29 0>; | ||
|
|
||
| phy-mode = "rmii"; | ||
| use-iram; | ||
| }; |
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