Skip to content

Commit

Permalink
Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Browse files Browse the repository at this point in the history 
Pull ARM fixes from Russell King:
 "A number of low impact fixes, the most noticable one is the thumb2
  frame pointer fix.  We also fix a regression caused during this merge
  window with ARM925 CPUs running with caches disabled, and fix a number
  of warnings"

* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
  ARM: arm925: ensure assembly sets up writethrough mapping
  ARM: perf: fix compiler warning with gcc 4.6.4 (and tidy code)
  ARM: l2c: fix dependencies on PL310 errata symbols
  ARM: 8069/1: Make thread_save_fp macro aware of THUMB2 mode
  ARM: 8068/1: scoop: Remove unused variable
  • Loading branch information
Linus Torvalds committed Jun 24, 2014
2 parents 8b8f5d9 + b8d8772 commit b4b664b
Show file tree
Hide file tree
Showing 10 changed files with 25 additions and 20 deletions.
1 change: 0 additions & 1 deletion arch/arm/common/scoop.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -182,7 +182,6 @@ static int scoop_probe(struct platform_device *pdev)
struct scoop_config *inf;
struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
int ret;
int temp;

if (!mem)
return -EINVAL;
Expand Down
6 changes: 6 additions & 0 deletions arch/arm/include/asm/thread_info.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -114,8 +114,14 @@ static inline struct thread_info *current_thread_info(void)
((unsigned long)(task_thread_info(tsk)->cpu_context.pc))
#define thread_saved_sp(tsk) \
((unsigned long)(task_thread_info(tsk)->cpu_context.sp))

#ifndef CONFIG_THUMB2_KERNEL
#define thread_saved_fp(tsk) \
((unsigned long)(task_thread_info(tsk)->cpu_context.fp))
#else
#define thread_saved_fp(tsk) \
((unsigned long)(task_thread_info(tsk)->cpu_context.r7))
#endif

extern void crunch_task_disable(struct thread_info *);
extern void crunch_task_copy(struct thread_info *, void *);
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/kernel/perf_event_v7.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1924,7 +1924,7 @@ static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc,
struct perf_event *event)
{
int idx;
int bit;
int bit = -1;
unsigned int prefix;
unsigned int region;
unsigned int code;
Expand Down Expand Up @@ -1953,7 +1953,7 @@ static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc,
}

idx = armv7pmu_get_event_idx(cpuc, event);
if (idx < 0 && krait_event)
if (idx < 0 && bit >= 0)
clear_bit(bit, cpuc->used_mask);

return idx;
Expand Down
12 changes: 6 additions & 6 deletions arch/arm/mach-imx/Kconfig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -734,9 +734,9 @@ config SOC_IMX6
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
select MFD_SYSCON
select PL310_ERRATA_588369 if CACHE_PL310
select PL310_ERRATA_727915 if CACHE_PL310
select PL310_ERRATA_769419 if CACHE_PL310
select PL310_ERRATA_588369 if CACHE_L2X0
select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0

config SOC_IMX6Q
bool "i.MX6 Quad/DualLite support"
Expand Down Expand Up @@ -771,9 +771,9 @@ config SOC_VF610
select ARM_GIC
select PINCTRL_VF610
select VF_PIT_TIMER
select PL310_ERRATA_588369 if CACHE_PL310
select PL310_ERRATA_727915 if CACHE_PL310
select PL310_ERRATA_769419 if CACHE_PL310
select PL310_ERRATA_588369 if CACHE_L2X0
select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0

help
This enable support for Freescale Vybrid VF610 processor.
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/mach-omap2/Kconfig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,8 +34,8 @@ config ARCH_OMAP4
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select OMAP_INTERCONNECT
select PL310_ERRATA_588369
select PL310_ERRATA_727915
select PL310_ERRATA_588369 if CACHE_L2X0
select PL310_ERRATA_727915 if CACHE_L2X0
select PM_OPP if PM
select PM_RUNTIME if CPU_IDLE
select ARM_ERRATA_754322
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/mach-sti/Kconfig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,8 +11,8 @@ menuconfig ARCH_STI
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_775420
select PL310_ERRATA_753970 if CACHE_PL310
select PL310_ERRATA_769419 if CACHE_PL310
select PL310_ERRATA_753970 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0
help
Include support for STiH41x SOCs like STiH415/416 using the device tree
for discovery
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/mach-ux500/Kconfig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ menuconfig ARCH_U8500
select PINCTRL
select PINCTRL_ABX500
select PINCTRL_NOMADIK
select PL310_ERRATA_753970 if CACHE_PL310
select PL310_ERRATA_753970 if CACHE_L2X0
help
Support for ST-Ericsson's Ux500 architecture

Expand Down
2 changes: 1 addition & 1 deletion arch/arm/mach-vexpress/Kconfig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
bool "Enable A5 and A9 only errata work-arounds"
default y
select ARM_ERRATA_720789
select PL310_ERRATA_753970 if CACHE_PL310
select PL310_ERRATA_753970 if CACHE_L2X0
help
Provides common dependencies for Versatile Express platforms
based on Cortex-A5 and Cortex-A9 processors. In order to
Expand Down
9 changes: 4 additions & 5 deletions arch/arm/mm/Kconfig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -889,17 +889,17 @@ config CACHE_L2X0
help
This option enables the L2x0 PrimeCell.

if CACHE_L2X0

config CACHE_PL310
bool
depends on CACHE_L2X0
default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
help
This option enables optimisations for the PL310 cache
controller.

config PL310_ERRATA_588369
bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
depends on CACHE_L2X0
help
The PL310 L2 cache controller implements three types of Clean &
Invalidate maintenance operations: by Physical Address
Expand All @@ -912,7 +912,6 @@ config PL310_ERRATA_588369

config PL310_ERRATA_727915
bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
depends on CACHE_L2X0
help
PL310 implements the Clean & Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that
Expand All @@ -923,7 +922,6 @@ config PL310_ERRATA_727915

config PL310_ERRATA_753970
bool "PL310 errata: cache sync operation may be faulty"
depends on CACHE_PL310
help
This option enables the workaround for the 753970 PL310 (r3p0) erratum.

Expand All @@ -938,7 +936,6 @@ config PL310_ERRATA_753970

config PL310_ERRATA_769419
bool "PL310 errata: no automatic Store Buffer drain"
depends on CACHE_L2X0
help
On revisions of the PL310 prior to r3p2, the Store Buffer does
not automatically drain. This can cause normal, non-cacheable
Expand All @@ -948,6 +945,8 @@ config PL310_ERRATA_769419
on systems with an outer cache, the store buffer is drained
explicitly.

endif

config CACHE_TAUROS2
bool "Enable the Tauros2 L2 cache controller"
depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
Expand Down
1 change: 1 addition & 0 deletions arch/arm/mm/proc-arm925.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -502,6 +502,7 @@ __\name\()_proc_info:
.long \cpu_val
.long \cpu_mask
.long PMD_TYPE_SECT | \
PMD_SECT_CACHEABLE | \
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
Expand Down

0 comments on commit b4b664b

Please sign in to comment.