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yaml
---
r: 102717
b: refs/heads/master
c: b8be63f
h: refs/heads/master
i:
  102715: bcb530d
v: v3
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Ivo van Doorn authored and John W. Linville committed May 22, 2008
1 parent 496ab41 commit b5b816f
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Showing 10 changed files with 224 additions and 308 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: dec13b6bda600c7e7da993e634562873112af50b
refs/heads/master: b8be63ffa5dc44324e7f507997870fa3e4b17619
78 changes: 39 additions & 39 deletions trunk/drivers/net/wireless/rt2x00/rt2400pci.c
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Original file line number Diff line number Diff line change
Expand Up @@ -620,39 +620,38 @@ static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
struct queue_entry *entry)
{
struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
u32 word;

rt2x00_desc_read(priv_rx->desc, 2, &word);
rt2x00_desc_read(entry_priv->desc, 2, &word);
rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
entry->queue->data_size);
rt2x00_desc_write(priv_rx->desc, 2, word);
rt2x00_desc_write(entry_priv->desc, 2, word);

rt2x00_desc_read(priv_rx->desc, 1, &word);
rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
rt2x00_desc_write(priv_rx->desc, 1, word);
rt2x00_desc_read(entry_priv->desc, 1, &word);
rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
rt2x00_desc_write(entry_priv->desc, 1, word);

rt2x00_desc_read(priv_rx->desc, 0, &word);
rt2x00_desc_read(entry_priv->desc, 0, &word);
rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
rt2x00_desc_write(priv_rx->desc, 0, word);
rt2x00_desc_write(entry_priv->desc, 0, word);
}

static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
struct queue_entry *entry)
{
struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
u32 word;

rt2x00_desc_read(priv_tx->desc, 0, &word);
rt2x00_desc_read(entry_priv->desc, 0, &word);
rt2x00_set_field32(&word, TXD_W0_VALID, 0);
rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
rt2x00_desc_write(priv_tx->desc, 0, word);
rt2x00_desc_write(entry_priv->desc, 0, word);
}

static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
{
struct queue_entry_priv_pci_rx *priv_rx;
struct queue_entry_priv_pci_tx *priv_tx;
struct queue_entry_priv_pci *entry_priv;
u32 reg;

/*
Expand All @@ -665,38 +664,39 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);

priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
priv_tx->desc_dma);
entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);

priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
priv_tx->desc_dma);
entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);

priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
priv_tx->desc_dma);
entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);

priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
priv_tx->desc_dma);
entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);

rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);

priv_rx = rt2x00dev->rx->entries[0].priv_data;
entry_priv = rt2x00dev->rx->entries[0].priv_data;
rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
entry_priv->desc_dma);
rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);

return 0;
Expand Down Expand Up @@ -995,7 +995,7 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
struct txentry_desc *txdesc)
{
struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
struct queue_entry_priv_pci_tx *entry_priv = skbdesc->entry->priv_data;
struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
__le32 *txd = skbdesc->desc;
u32 word;

Expand Down Expand Up @@ -1078,14 +1078,14 @@ static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
static void rt2400pci_fill_rxdone(struct queue_entry *entry,
struct rxdone_entry_desc *rxdesc)
{
struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
u32 word0;
u32 word2;
u32 word3;

rt2x00_desc_read(priv_rx->desc, 0, &word0);
rt2x00_desc_read(priv_rx->desc, 2, &word2);
rt2x00_desc_read(priv_rx->desc, 3, &word3);
rt2x00_desc_read(entry_priv->desc, 0, &word0);
rt2x00_desc_read(entry_priv->desc, 2, &word2);
rt2x00_desc_read(entry_priv->desc, 3, &word3);

if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
Expand Down Expand Up @@ -1114,15 +1114,15 @@ static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
const enum data_queue_qid queue_idx)
{
struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
struct queue_entry_priv_pci_tx *priv_tx;
struct queue_entry_priv_pci *entry_priv;
struct queue_entry *entry;
struct txdone_entry_desc txdesc;
u32 word;

while (!rt2x00queue_empty(queue)) {
entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
priv_tx = entry->priv_data;
rt2x00_desc_read(priv_tx->desc, 0, &word);
entry_priv = entry->priv_data;
rt2x00_desc_read(entry_priv->desc, 0, &word);

if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
!rt2x00_get_field32(word, TXD_W0_VALID))
Expand Down Expand Up @@ -1489,14 +1489,14 @@ static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
{
struct rt2x00_dev *rt2x00dev = hw->priv;
struct rt2x00_intf *intf = vif_to_intf(control->vif);
struct queue_entry_priv_pci_tx *priv_tx;
struct queue_entry_priv_pci *entry_priv;
struct skb_frame_desc *skbdesc;
struct txentry_desc txdesc;
u32 reg;

if (unlikely(!intf->beacon))
return -ENOBUFS;
priv_tx = intf->beacon->priv_data;
entry_priv = intf->beacon->priv_data;

/*
* Copy all TX descriptor information into txdesc,
Expand All @@ -1514,7 +1514,7 @@ static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
skbdesc->data = skb->data;
skbdesc->data_len = skb->len;
skbdesc->desc = priv_tx->desc;
skbdesc->desc = entry_priv->desc;
skbdesc->desc_len = intf->beacon->queue->desc_size;
skbdesc->entry = intf->beacon;

Expand All @@ -1533,7 +1533,7 @@ static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
* Write entire beacon with descriptor to register,
* and kick the beacon generator.
*/
memcpy(priv_tx->data, skb->data, skb->len);
memcpy(entry_priv->data, skb->data, skb->len);
rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);

Expand Down Expand Up @@ -1594,28 +1594,28 @@ static const struct data_queue_desc rt2400pci_queue_rx = {
.entry_num = RX_ENTRIES,
.data_size = DATA_FRAME_SIZE,
.desc_size = RXD_DESC_SIZE,
.priv_size = sizeof(struct queue_entry_priv_pci_rx),
.priv_size = sizeof(struct queue_entry_priv_pci),
};

static const struct data_queue_desc rt2400pci_queue_tx = {
.entry_num = TX_ENTRIES,
.data_size = DATA_FRAME_SIZE,
.desc_size = TXD_DESC_SIZE,
.priv_size = sizeof(struct queue_entry_priv_pci_tx),
.priv_size = sizeof(struct queue_entry_priv_pci),
};

static const struct data_queue_desc rt2400pci_queue_bcn = {
.entry_num = BEACON_ENTRIES,
.data_size = MGMT_FRAME_SIZE,
.desc_size = TXD_DESC_SIZE,
.priv_size = sizeof(struct queue_entry_priv_pci_tx),
.priv_size = sizeof(struct queue_entry_priv_pci),
};

static const struct data_queue_desc rt2400pci_queue_atim = {
.entry_num = ATIM_ENTRIES,
.data_size = DATA_FRAME_SIZE,
.desc_size = TXD_DESC_SIZE,
.priv_size = sizeof(struct queue_entry_priv_pci_tx),
.priv_size = sizeof(struct queue_entry_priv_pci),
};

static const struct rt2x00_ops rt2400pci_ops = {
Expand Down
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