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staging: brcm80211: further simplified register access macro's
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The SELECT_BUS_READ and SELECT_BUS_WRITE macro's always select
a (sdio) bus operation for fullmac, and a memory operation for
softmac. Thus they can be removed by expanding them in place.

Signed-off-by: Roland Vossen <rvossen@broadcom.com>
Reviewed-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Roland Vossen authored and Greg Kroah-Hartman committed Jun 7, 2011
1 parent 4489518 commit b61a4be
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Showing 2 changed files with 61 additions and 157 deletions.
102 changes: 14 additions & 88 deletions drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,102 +39,30 @@
#endif
#endif

#if defined(BCMSDIO)
#define SELECT_BUS_WRITE(mmap_op, bus_op) bus_op
#define SELECT_BUS_READ(mmap_op, bus_op) bus_op
#else
#define SELECT_BUS_WRITE(mmap_op, bus_op) mmap_op
#define SELECT_BUS_READ(mmap_op, bus_op) mmap_op
#endif

/* register access macros */
#ifndef __BIG_ENDIAN
#ifndef __mips__
#define R_REG(r) (\
SELECT_BUS_READ(sizeof(*(r)) == sizeof(u8) ? \
readb((volatile u8*)(r)) : \
sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
readl((volatile u32*)(r)), bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \
)
#define R_REG(r) \
bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))
#else /* __mips__ */
#define R_REG(r) (\
SELECT_BUS_READ( \
({ \
__typeof(*(r)) __osl_v; \
__asm__ __volatile__("sync"); \
switch (sizeof(*(r))) { \
case sizeof(u8): \
__osl_v = readb((volatile u8*)(r)); \
break; \
case sizeof(u16): \
__osl_v = readw((volatile u16*)(r)); \
break; \
case sizeof(u32): \
__osl_v = \
readl((volatile u32*)(r)); \
break; \
} \
__asm__ __volatile__("sync"); \
__osl_v; \
}), \
({ \
__typeof(*(r)) __osl_v; \
__asm__ __volatile__("sync"); \
__osl_v = bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r)); \
__asm__ __volatile__("sync"); \
__osl_v; \
})) \
)
#define R_REG(r) \
({ \
__typeof(*(r)) __osl_v; \
__asm__ __volatile__("sync"); \
__osl_v = bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r)); \
__asm__ __volatile__("sync"); \
__osl_v; \
})
#endif /* __mips__ */

#define W_REG(r, v) do { \
SELECT_BUS_WRITE( \
switch (sizeof(*(r))) { \
case sizeof(u8): \
writeb((u8)(v), (volatile u8*)(r)); break; \
case sizeof(u16): \
writew((u16)(v), (volatile u16*)(r)); break; \
case sizeof(u32): \
writel((u32)(v), (volatile u32*)(r)); break; \
}, \
bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), (v))); \
bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), (v)); \
} while (0)
#else /* __BIG_ENDIAN */
#define R_REG(r) (\
SELECT_BUS_READ( \
({ \
__typeof(*(r)) __osl_v; \
switch (sizeof(*(r))) { \
case sizeof(u8): \
__osl_v = \
readb((volatile u8*)((r)^3)); \
break; \
case sizeof(u16): \
__osl_v = \
readw((volatile u16*)((r)^2)); \
break; \
case sizeof(u32): \
__osl_v = readl((volatile u32*)(r)); \
break; \
} \
__osl_v; \
}), \
bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \
)
#define R_REG(r) \
bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))
#define W_REG(r, v) do { \
SELECT_BUS_WRITE( \
switch (sizeof(*(r))) { \
case sizeof(u8): \
writeb((u8)(v), \
(volatile u8*)((r)^3)); break; \
case sizeof(u16): \
writew((u16)(v), \
(volatile u16*)((r)^2)); break; \
case sizeof(u32): \
writel((u32)(v), \
(volatile u32*)(r)); break; \
}, \
bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), v)); \
bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), v); \
} while (0)
#endif /* __BIG_ENDIAN */

Expand All @@ -155,8 +83,6 @@
#define SET_REG(r, mask, val) \
W_REG((r), ((R_REG(r) & ~(mask)) | (val)))



#ifdef DHD_DEBUG

/* ARM trap handling */
Expand Down
116 changes: 47 additions & 69 deletions drivers/staging/brcm80211/brcmsmac/wlc_types.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -48,90 +48,69 @@ do { \
#endif
#endif

#if defined(BCMSDIO)
#define SELECT_BUS_WRITE(mmap_op, bus_op) bus_op
#define SELECT_BUS_READ(mmap_op, bus_op) bus_op
#else
#define SELECT_BUS_WRITE(mmap_op, bus_op) mmap_op
#define SELECT_BUS_READ(mmap_op, bus_op) mmap_op
#endif

/* register access macros */
#ifndef __BIG_ENDIAN
#ifndef __mips__
#define R_REG(r) (\
SELECT_BUS_READ(sizeof(*(r)) == sizeof(u8) ? \
readb((volatile u8*)(r)) : \
sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
readl((volatile u32*)(r)), bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \
)
#define R_REG(r) \
({\
sizeof(*(r)) == sizeof(u8) ? \
readb((volatile u8*)(r)) : \
sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
readl((volatile u32*)(r)); \
})
#else /* __mips__ */
#define R_REG(r) (\
SELECT_BUS_READ( \
({ \
__typeof(*(r)) __osl_v; \
__asm__ __volatile__("sync"); \
switch (sizeof(*(r))) { \
case sizeof(u8): \
__osl_v = readb((volatile u8*)(r)); \
break; \
case sizeof(u16): \
__osl_v = readw((volatile u16*)(r)); \
break; \
case sizeof(u32): \
__osl_v = \
readl((volatile u32*)(r)); \
break; \
} \
__asm__ __volatile__("sync"); \
__osl_v; \
}), \
({ \
__typeof(*(r)) __osl_v; \
__asm__ __volatile__("sync"); \
__osl_v = bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r)); \
__asm__ __volatile__("sync"); \
__osl_v; \
})) \
)
#define R_REG(r) \
({ \
__typeof(*(r)) __osl_v; \
__asm__ __volatile__("sync"); \
switch (sizeof(*(r))) { \
case sizeof(u8): \
__osl_v = readb((volatile u8*)(r)); \
break; \
case sizeof(u16): \
__osl_v = readw((volatile u16*)(r)); \
break; \
case sizeof(u32): \
__osl_v = \
readl((volatile u32*)(r)); \
break; \
} \
__asm__ __volatile__("sync"); \
__osl_v; \
})
#endif /* __mips__ */

#define W_REG(r, v) do { \
SELECT_BUS_WRITE( \
switch (sizeof(*(r))) { \
case sizeof(u8): \
writeb((u8)(v), (volatile u8*)(r)); break; \
case sizeof(u16): \
writew((u16)(v), (volatile u16*)(r)); break; \
case sizeof(u32): \
writel((u32)(v), (volatile u32*)(r)); break; \
}, \
bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), (v))); \
}; \
} while (0)
#else /* __BIG_ENDIAN */
#define R_REG(r) (\
SELECT_BUS_READ( \
({ \
__typeof(*(r)) __osl_v; \
switch (sizeof(*(r))) { \
case sizeof(u8): \
__osl_v = \
readb((volatile u8*)((r)^3)); \
break; \
case sizeof(u16): \
__osl_v = \
readw((volatile u16*)((r)^2)); \
break; \
case sizeof(u32): \
__osl_v = readl((volatile u32*)(r)); \
break; \
} \
__osl_v; \
}), \
bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \
)
#define R_REG(r) \
({ \
__typeof(*(r)) __osl_v; \
switch (sizeof(*(r))) { \
case sizeof(u8): \
__osl_v = \
readb((volatile u8*)((r)^3)); \
break; \
case sizeof(u16): \
__osl_v = \
readw((volatile u16*)((r)^2)); \
break; \
case sizeof(u32): \
__osl_v = readl((volatile u32*)(r)); \
break; \
} \
__osl_v; \
})

#define W_REG(r, v) do { \
SELECT_BUS_WRITE( \
switch (sizeof(*(r))) { \
case sizeof(u8): \
writeb((u8)(v), \
Expand All @@ -142,8 +121,7 @@ do { \
case sizeof(u32): \
writel((u32)(v), \
(volatile u32*)(r)); break; \
}, \
bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), v)); \
} \
} while (0)
#endif /* __BIG_ENDIAN */

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