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drm/i915: get rid of primary_enabled and use atomic state
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This was an optimization from way back before we had primary plane
support to be able to disable the primary plane. But with primary
plane support userspace can tell the kernel this directly, so there's
no big need for this any more. And it's getting in the way of the
atomic conversion.

If need be we can resurrect this later on properly again.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
[danvet: Explain why removing this is ok.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Maarten Lankhorst authored and Daniel Vetter committed May 8, 2015
1 parent 27321ae commit b70709a
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Showing 3 changed files with 29 additions and 24 deletions.
50 changes: 28 additions & 22 deletions drivers/gpu/drm/i915/intel_display.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2236,11 +2236,7 @@ static void intel_enable_primary_hw_plane(struct drm_plane *plane,

/* If the pipe isn't enabled, we can't pump pixels and may hang */
assert_pipe_enabled(dev_priv, intel_crtc->pipe);

if (intel_crtc->primary_enabled)
return;

intel_crtc->primary_enabled = true;
to_intel_plane_state(plane->state)->visible = true;

dev_priv->display.update_primary_plane(crtc, plane->fb,
crtc->x, crtc->y);
Expand Down Expand Up @@ -2661,14 +2657,16 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_plane *primary = crtc->primary;
bool visible = to_intel_plane_state(primary->state)->visible;
struct drm_i915_gem_object *obj;
int plane = intel_crtc->plane;
unsigned long linear_offset;
u32 dspcntr;
u32 reg = DSPCNTR(plane);
int pixel_size;

if (!intel_crtc->primary_enabled || !fb) {
if (!visible || !fb) {
I915_WRITE(reg, 0);
if (INTEL_INFO(dev)->gen >= 4)
I915_WRITE(DSPSURF(plane), 0);
Expand Down Expand Up @@ -2790,14 +2788,16 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_plane *primary = crtc->primary;
bool visible = to_intel_plane_state(primary->state)->visible;
struct drm_i915_gem_object *obj;
int plane = intel_crtc->plane;
unsigned long linear_offset;
u32 dspcntr;
u32 reg = DSPCNTR(plane);
int pixel_size;

if (!intel_crtc->primary_enabled || !fb) {
if (!visible || !fb) {
I915_WRITE(reg, 0);
I915_WRITE(DSPSURF(plane), 0);
POSTING_READ(reg);
Expand Down Expand Up @@ -3059,24 +3059,24 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_plane *plane = crtc->primary;
bool visible = to_intel_plane_state(plane->state)->visible;
struct drm_i915_gem_object *obj;
int pipe = intel_crtc->pipe;
u32 plane_ctl, stride_div, stride;
u32 tile_height, plane_offset, plane_size;
unsigned int rotation;
int x_offset, y_offset;
unsigned long surf_addr;
struct drm_plane *plane;
struct intel_crtc_state *crtc_state = intel_crtc->config;
struct intel_plane_state *plane_state;
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
int scaler_id = -1;

plane = crtc->primary;
plane_state = to_intel_plane_state(plane->state);

if (!intel_crtc->primary_enabled || !fb) {
if (!visible || !fb) {
I915_WRITE(PLANE_CTL(pipe, 0), 0);
I915_WRITE(PLANE_SURF(pipe, 0), 0);
POSTING_READ(PLANE_CTL(pipe, 0));
Expand Down Expand Up @@ -4783,7 +4783,6 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
hsw_disable_ips(intel_crtc);

intel_crtc_dpms_overlay(intel_crtc, false);
intel_crtc->primary_enabled = false;
for_each_intel_plane(dev, intel_plane) {
if (intel_plane->pipe == pipe) {
struct drm_crtc *from = intel_plane->base.crtc;
Expand Down Expand Up @@ -12891,6 +12890,9 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
} else if (config->fb_changed) {
struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
struct drm_plane *primary = set->crtc->primary;
struct intel_plane_state *plane_state =
to_intel_plane_state(primary->state);
bool was_visible = plane_state->visible;
int vdisplay, hdisplay;

drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
Expand All @@ -12903,7 +12905,8 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
* We need to make sure the primary plane is re-enabled if it
* has previously been turned off.
*/
if (!intel_crtc->primary_enabled && ret == 0) {
plane_state = to_intel_plane_state(primary->state);
if (ret == 0 && !was_visible && plane_state->visible) {
WARN_ON(!intel_crtc->active);
intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
}
Expand Down Expand Up @@ -13239,6 +13242,9 @@ intel_check_primary_plane(struct drm_plane *plane,
return ret;

if (intel_crtc->active) {
struct intel_plane_state *old_state =
to_intel_plane_state(plane->state);

intel_crtc->atomic.wait_for_flips = true;

/*
Expand All @@ -13251,20 +13257,20 @@ intel_check_primary_plane(struct drm_plane *plane,
* one is done too late. We eventually need to unify
* this.
*/
if (intel_crtc->primary_enabled &&
if (state->visible &&
INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
dev_priv->fbc.crtc == intel_crtc &&
state->base.rotation != BIT(DRM_ROTATE_0)) {
intel_crtc->atomic.disable_fbc = true;
}

if (state->visible) {
if (state->visible && !old_state->visible) {
/*
* BDW signals flip done immediately if the plane
* is disabled, even if the plane enable is already
* armed to occur at the next vblank :(
*/
if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
if (IS_BROADWELL(dev))
intel_crtc->atomic.wait_vblank = true;
}

Expand Down Expand Up @@ -13306,8 +13312,6 @@ intel_commit_primary_plane(struct drm_plane *plane,
crtc->y = src->y1 >> 16;

if (intel_crtc->active) {
intel_crtc->primary_enabled = state->visible;

if (state->visible)
/* FIXME: kill this fastboot hack */
intel_update_pipe_size(intel_crtc);
Expand All @@ -13325,9 +13329,6 @@ intel_disable_primary_plane(struct drm_plane *plane,
struct drm_device *dev = plane->dev;
struct drm_i915_private *dev_priv = dev->dev_private;

if (!force)
to_intel_crtc(crtc)->primary_enabled = false;

dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
}

Expand Down Expand Up @@ -14791,8 +14792,8 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
* Temporarily change the plane mapping and disable everything
* ... */
plane = crtc->plane;
to_intel_plane_state(crtc->base.primary->state)->visible = true;
crtc->plane = !plane;
crtc->primary_enabled = true;
dev_priv->display.crtc_disable(&crtc->base);
crtc->plane = plane;

Expand Down Expand Up @@ -14969,6 +14970,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
int i;

for_each_intel_crtc(dev, crtc) {
struct drm_plane *primary = crtc->base.primary;
struct intel_plane_state *plane_state;

memset(crtc->config, 0, sizeof(*crtc->config));

crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
Expand All @@ -14978,7 +14982,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)

crtc->base.state->enable = crtc->active;
crtc->base.enabled = crtc->active;
crtc->primary_enabled = primary_get_hw_state(crtc);

plane_state = to_intel_plane_state(primary->state);
plane_state->visible = primary_get_hw_state(crtc);

DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
crtc->base.base.id,
Expand Down
1 change: 0 additions & 1 deletion drivers/gpu/drm/i915/intel_drv.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -507,7 +507,6 @@ struct intel_crtc {
*/
bool active;
unsigned long enabled_power_domains;
bool primary_enabled; /* is the primary plane (partially) visible? */
bool lowfreq_avail;
struct intel_overlay *overlay;
struct intel_unpin_work *unpin_work;
Expand Down
2 changes: 1 addition & 1 deletion drivers/gpu/drm/i915/intel_fbc.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -457,7 +457,7 @@ static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv)
tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe];

if (intel_crtc_active(tmp_crtc) &&
to_intel_crtc(tmp_crtc)->primary_enabled) {
to_intel_plane_state(tmp_crtc->primary->state)->visible) {
if (one_pipe_only && crtc) {
if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
Expand Down

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