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yaml
---
r: 108404
b: refs/heads/master
c: 17de50b
h: refs/heads/master
v: v3
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Eilon Greenstein authored and David S. Miller committed Aug 13, 2008
1 parent 7513c27 commit b7e2cea
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Showing 4 changed files with 52 additions and 44 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 8c99e7b0436473593a68e740d1032909bc5335a1
refs/heads/master: 17de50b7f71d176375e9d4d67ffce42482e5515f
2 changes: 1 addition & 1 deletion trunk/drivers/net/bnx2x.h
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Original file line number Diff line number Diff line change
Expand Up @@ -924,7 +924,7 @@ struct bnx2x {
void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
u32 len32);
int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);

static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
int wait)
Expand Down
78 changes: 43 additions & 35 deletions trunk/drivers/net/bnx2x_link.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1842,15 +1842,15 @@ static u8 bnx2x_emac_program(struct link_params *params,
}

/*****************************************************************************/
/* External Phy section */
/* External Phy section */
/*****************************************************************************/
static void bnx2x_hw_reset(struct bnx2x *bp)
static void bnx2x_hw_reset(struct bnx2x *bp, u8 port)
{
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_OUTPUT_LOW);
MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
msleep(1);
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_OUTPUT_HIGH);
MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
}

static void bnx2x_ext_phy_reset(struct link_params *params,
Expand Down Expand Up @@ -1879,10 +1879,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params,

/* Restore normal power mode*/
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_HIGH);
MISC_REGISTERS_GPIO_OUTPUT_HIGH,
params->port);

/* HW reset */
bnx2x_hw_reset(bp);
bnx2x_hw_reset(bp, params->port);

bnx2x_cl45_write(bp, params->port,
ext_phy_type,
Expand All @@ -1894,7 +1895,8 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
/* Unset Low Power Mode and SW reset */
/* Restore normal power mode*/
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_HIGH);
MISC_REGISTERS_GPIO_OUTPUT_HIGH,
params->port);

DP(NETIF_MSG_LINK, "XGXS 8072\n");
bnx2x_cl45_write(bp, params->port,
Expand All @@ -1912,19 +1914,14 @@ static void bnx2x_ext_phy_reset(struct link_params *params,

/* Restore normal power mode*/
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_HIGH);
MISC_REGISTERS_GPIO_OUTPUT_HIGH,
params->port);

bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_OUTPUT_HIGH);
MISC_REGISTERS_GPIO_OUTPUT_HIGH,
params->port);

DP(NETIF_MSG_LINK, "XGXS 8073\n");
bnx2x_cl45_write(bp,
params->port,
ext_phy_type,
ext_phy_addr,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_CTRL,
1<<15);
}
break;

Expand All @@ -1933,10 +1930,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params,

/* Restore normal power mode*/
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_HIGH);
MISC_REGISTERS_GPIO_OUTPUT_HIGH,
params->port);

/* HW reset */
bnx2x_hw_reset(bp);
bnx2x_hw_reset(bp, params->port);

break;

Expand All @@ -1959,7 +1957,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params,

case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
DP(NETIF_MSG_LINK, "SerDes 5482\n");
bnx2x_hw_reset(bp);
bnx2x_hw_reset(bp, params->port);
break;

default:
Expand Down Expand Up @@ -3286,12 +3284,14 @@ static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr,

/* take ext phy out of reset */
bnx2x_set_gpio(bp,
MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_HIGH);
MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_HIGH,
port);

bnx2x_set_gpio(bp,
MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_HIGH);
MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_HIGH,
port);

/* wait for 5ms */
msleep(5);
Expand All @@ -3311,13 +3311,17 @@ static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr,
}
}

static void bnx2x_turn_off_sf(struct bnx2x *bp)
static void bnx2x_turn_off_sf(struct bnx2x *bp, u8 port)
{
/* put sf to reset */
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, MISC_REGISTERS_GPIO_LOW);
bnx2x_set_gpio(bp,
MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_LOW);
MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_LOW,
port);
bnx2x_set_gpio(bp,
MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_LOW,
port);
}

u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
Expand Down Expand Up @@ -3371,7 +3375,7 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
version[4] = '\0';

if (!driver_loaded)
bnx2x_turn_off_sf(bp);
bnx2x_turn_off_sf(bp, params->port);
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
Expand Down Expand Up @@ -4013,10 +4017,12 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars)
/* HW reset */

bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_OUTPUT_LOW);
MISC_REGISTERS_GPIO_OUTPUT_LOW,
port);

bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_LOW);
MISC_REGISTERS_GPIO_OUTPUT_LOW,
port);

DP(NETIF_MSG_LINK, "reset external PHY\n");
} else if (ext_phy_type ==
Expand All @@ -4025,7 +4031,8 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars)
"low power mode\n",
port);
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_LOW);
MISC_REGISTERS_GPIO_OUTPUT_LOW,
port);
}
}
/* reset the SerDes/XGXS */
Expand Down Expand Up @@ -4271,7 +4278,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
and issuing a reset.*/

bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
MISC_REGISTERS_GPIO_HIGH);
MISC_REGISTERS_GPIO_HIGH, port);

bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);

Expand Down Expand Up @@ -4503,15 +4510,16 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
}

/* DSP Remove Download Mode */
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, MISC_REGISTERS_GPIO_LOW);
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
MISC_REGISTERS_GPIO_LOW, port);

bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);

/* wait 0.5 sec to allow it to run */
for (cnt = 0; cnt < 100; cnt++)
msleep(5);

bnx2x_hw_reset(bp);
bnx2x_hw_reset(bp, port);

for (cnt = 0; cnt < 100; cnt++)
msleep(5);
Expand Down Expand Up @@ -4586,7 +4594,7 @@ u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr,
data, size);
if (!driver_loaded)
bnx2x_turn_off_sf(bp);
bnx2x_turn_off_sf(bp, port);
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
Expand Down
14 changes: 7 additions & 7 deletions trunk/drivers/net/bnx2x_main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1788,11 +1788,11 @@ static void bnx2x_release_phy_lock(struct bnx2x *bp)
mutex_unlock(&bp->port.phy_mutex);
}

int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
{
/* The GPIO should be swapped if swap register is set and active */
int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ BP_PORT(bp);
REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
int gpio_shift = gpio_num +
(gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
u32 gpio_mask = (1 << gpio_shift);
Expand Down Expand Up @@ -1824,7 +1824,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
break;

case MISC_REGISTERS_GPIO_INPUT_HI_Z :
case MISC_REGISTERS_GPIO_INPUT_HI_Z:
DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
gpio_num, gpio_shift);
/* set FLOAT */
Expand Down Expand Up @@ -2553,12 +2553,12 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
/* Fan failure attention */

/* The PHY reset is controled by GPIO 1 */
/* The PHY reset is controlled by GPIO 1 */
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
MISC_REGISTERS_GPIO_OUTPUT_LOW);
/* Low power mode is controled by GPIO 2 */
MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
/* Low power mode is controlled by GPIO 2 */
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_LOW);
MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
/* mark the failure */
bp->link_params.ext_phy_config &=
~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
Expand Down

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