-
Notifications
You must be signed in to change notification settings - Fork 0
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
yaml --- r: 66171 b: refs/heads/master c: baf22c1 h: refs/heads/master i: 66169: e75559d 66167: a611fcd v: v3
- Loading branch information
Ralf Baechle
committed
Oct 11, 2007
1 parent
3ebb04f
commit b813ebf
Showing
25 changed files
with
626 additions
and
98 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,2 +1,2 @@ | ||
| --- | ||
| refs/heads/master: 21c854dcbd7698bf723676a552968040e2813490 | ||
| refs/heads/master: baf22c1e7aedf264e264b15d2595e5e76564bd4e |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_AU1X00_WAR_H | ||
| #define __ASM_MIPS_MACH_AU1X00_WAR_H | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| #define MIPS_CACHE_SYNC_WAR 0 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 0 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
| #define R10000_LLSC_WAR 0 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */ |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_BCM947XX_WAR_H | ||
| #define __ASM_MIPS_MACH_BCM947XX_WAR_H | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| #define MIPS_CACHE_SYNC_WAR 0 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 0 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
| #define R10000_LLSC_WAR 0 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_BCM947XX_WAR_H */ |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_COBALT_WAR_H | ||
| #define __ASM_MIPS_MACH_COBALT_WAR_H | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| #define MIPS_CACHE_SYNC_WAR 0 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 0 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
| #define R10000_LLSC_WAR 0 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_COBALT_WAR_H */ |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_DEC_WAR_H | ||
| #define __ASM_MIPS_MACH_DEC_WAR_H | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| #define MIPS_CACHE_SYNC_WAR 0 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 0 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
| #define R10000_LLSC_WAR 0 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_DEC_WAR_H */ |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_EMMA2RH_WAR_H | ||
| #define __ASM_MIPS_MACH_EMMA2RH_WAR_H | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| #define MIPS_CACHE_SYNC_WAR 0 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 0 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
| #define R10000_LLSC_WAR 0 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_EMMA2RH_WAR_H */ |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_EXCITE_WAR_H | ||
| #define __ASM_MIPS_MACH_EXCITE_WAR_H | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| #define MIPS_CACHE_SYNC_WAR 0 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 1 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 1 | ||
| #define R10000_LLSC_WAR 0 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */ |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,29 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_IP22_WAR_H | ||
| #define __ASM_MIPS_MACH_IP22_WAR_H | ||
|
|
||
| /* | ||
| * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. | ||
| */ | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 1 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 1 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 1 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| #define MIPS_CACHE_SYNC_WAR 0 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 0 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
| #define R10000_LLSC_WAR 0 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_IP22_WAR_H */ |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_IP27_WAR_H | ||
| #define __ASM_MIPS_MACH_IP27_WAR_H | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| #define MIPS_CACHE_SYNC_WAR 0 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 0 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
| #define R10000_LLSC_WAR 1 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_IP27_WAR_H */ |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_IP32_WAR_H | ||
| #define __ASM_MIPS_MACH_IP32_WAR_H | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| #define MIPS_CACHE_SYNC_WAR 0 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 0 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 1 | ||
| #define R10000_LLSC_WAR 0 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_IP32_WAR_H */ |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_JAZZ_WAR_H | ||
| #define __ASM_MIPS_MACH_JAZZ_WAR_H | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| #define MIPS_CACHE_SYNC_WAR 0 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 0 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
| #define R10000_LLSC_WAR 0 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_JAZZ_WAR_H */ |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_JMR3927_WAR_H | ||
| #define __ASM_MIPS_MACH_JMR3927_WAR_H | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| #define MIPS_CACHE_SYNC_WAR 0 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 0 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
| #define R10000_LLSC_WAR 0 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_JMR3927_WAR_H */ |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_LASAT_WAR_H | ||
| #define __ASM_MIPS_MACH_LASAT_WAR_H | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| #define MIPS_CACHE_SYNC_WAR 0 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 0 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
| #define R10000_LLSC_WAR 0 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_LASAT_WAR_H */ |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_LEMOTE_WAR_H | ||
| #define __ASM_MIPS_MACH_LEMOTE_WAR_H | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| #define MIPS_CACHE_SYNC_WAR 0 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 0 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
| #define R10000_LLSC_WAR 0 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_LEMOTE_WAR_H */ |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_MIPS_WAR_H | ||
| #define __ASM_MIPS_MACH_MIPS_WAR_H | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 1 | ||
| #define MIPS_CACHE_SYNC_WAR 1 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 0 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 1 | ||
| #define R10000_LLSC_WAR 0 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| * | ||
| * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| */ | ||
| #ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H | ||
| #define __ASM_MIPS_MACH_MIPSSIM_WAR_H | ||
|
|
||
| #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| #define R5432_CP0_INTERRUPT_WAR 0 | ||
| #define BCM1250_M3_WAR 0 | ||
| #define SIBYTE_1956_WAR 0 | ||
| #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| #define MIPS_CACHE_SYNC_WAR 0 | ||
| #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| #define RM9000_CDEX_SMP_WAR 0 | ||
| #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
| #define R10000_LLSC_WAR 0 | ||
| #define MIPS34K_MISSED_ITLB_WAR 0 | ||
|
|
||
| #endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */ |
Oops, something went wrong.