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yaml
---
r: 210198
b: refs/heads/master
c: a69ffdb
h: refs/heads/master
v: v3
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Zhenyu Wang authored and Chris Wilson committed Sep 7, 2010
1 parent 71be086 commit b8fb4c5
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Showing 3 changed files with 8 additions and 3 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337
refs/heads/master: a69ffdbfcba8eabf2ca9d384b578e6f28b339c61
1 change: 1 addition & 0 deletions trunk/drivers/gpu/drm/i915/i915_reg.h
Original file line number Diff line number Diff line change
Expand Up @@ -319,6 +319,7 @@

#define MI_MODE 0x0209c
# define VS_TIMER_DISPATCH (1 << 6)
# define MI_FLUSH_ENABLE (1 << 11)

#define SCPD0 0x0209c /* 915+ only */
#define IER 0x020a0
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8 changes: 6 additions & 2 deletions trunk/drivers/gpu/drm/i915/intel_ringbuffer.c
Original file line number Diff line number Diff line change
Expand Up @@ -220,9 +220,13 @@ static int init_render_ring(struct drm_device *dev,
{
drm_i915_private_t *dev_priv = dev->dev_private;
int ret = init_ring_common(dev, ring);
int mode;

if (IS_I9XX(dev) && !IS_GEN3(dev)) {
I915_WRITE(MI_MODE,
(VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH);
mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
if (IS_GEN6(dev))
mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
I915_WRITE(MI_MODE, mode);
}
return ret;
}
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