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yaml
---
r: 268925
b: refs/heads/master
c: 6b2c180
h: refs/heads/master
i:
  268923: bed2b88
v: v3
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Thomas Gleixner authored and Ingo Molnar committed Sep 13, 2011
1 parent 756762f commit ba0d0fe
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Showing 2 changed files with 22 additions and 22 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 757455d41c390da4ae8e06468ad097fe42eaab41
refs/heads/master: 6b2c1800f1d3a608af952cfbd57f8f1a71c5d9b4
42 changes: 21 additions & 21 deletions trunk/drivers/video/console/vgacon.c
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Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@
#include <video/vga.h>
#include <asm/io.h>

static DEFINE_SPINLOCK(vga_lock);
static DEFINE_RAW_SPINLOCK(vga_lock);
static int cursor_size_lastfrom;
static int cursor_size_lastto;
static u32 vgacon_xres;
Expand Down Expand Up @@ -157,7 +157,7 @@ static inline void write_vga(unsigned char reg, unsigned int val)
* ddprintk might set the console position from interrupt
* handlers, thus the write has to be IRQ-atomic.
*/
spin_lock_irqsave(&vga_lock, flags);
raw_spin_lock_irqsave(&vga_lock, flags);

#ifndef SLOW_VGA
v1 = reg + (val & 0xff00);
Expand All @@ -170,7 +170,7 @@ static inline void write_vga(unsigned char reg, unsigned int val)
outb_p(reg + 1, vga_video_port_reg);
outb_p(val & 0xff, vga_video_port_val);
#endif
spin_unlock_irqrestore(&vga_lock, flags);
raw_spin_unlock_irqrestore(&vga_lock, flags);
}

static inline void vga_set_mem_top(struct vc_data *c)
Expand Down Expand Up @@ -664,7 +664,7 @@ static void vgacon_set_cursor_size(int xpos, int from, int to)
cursor_size_lastfrom = from;
cursor_size_lastto = to;

spin_lock_irqsave(&vga_lock, flags);
raw_spin_lock_irqsave(&vga_lock, flags);
if (vga_video_type >= VIDEO_TYPE_VGAC) {
outb_p(VGA_CRTC_CURSOR_START, vga_video_port_reg);
curs = inb_p(vga_video_port_val);
Expand All @@ -682,7 +682,7 @@ static void vgacon_set_cursor_size(int xpos, int from, int to)
outb_p(curs, vga_video_port_val);
outb_p(VGA_CRTC_CURSOR_END, vga_video_port_reg);
outb_p(cure, vga_video_port_val);
spin_unlock_irqrestore(&vga_lock, flags);
raw_spin_unlock_irqrestore(&vga_lock, flags);
}

static void vgacon_cursor(struct vc_data *c, int mode)
Expand Down Expand Up @@ -757,7 +757,7 @@ static int vgacon_doresize(struct vc_data *c,
unsigned int scanlines = height * c->vc_font.height;
u8 scanlines_lo = 0, r7 = 0, vsync_end = 0, mode, max_scan;

spin_lock_irqsave(&vga_lock, flags);
raw_spin_lock_irqsave(&vga_lock, flags);

vgacon_xres = width * VGA_FONTWIDTH;
vgacon_yres = height * c->vc_font.height;
Expand Down Expand Up @@ -808,7 +808,7 @@ static int vgacon_doresize(struct vc_data *c,
outb_p(vsync_end, vga_video_port_val);
}

spin_unlock_irqrestore(&vga_lock, flags);
raw_spin_unlock_irqrestore(&vga_lock, flags);
return 0;
}

Expand Down Expand Up @@ -891,11 +891,11 @@ static void vga_vesa_blank(struct vgastate *state, int mode)
{
/* save original values of VGA controller registers */
if (!vga_vesa_blanked) {
spin_lock_irq(&vga_lock);
raw_spin_lock_irq(&vga_lock);
vga_state.SeqCtrlIndex = vga_r(state->vgabase, VGA_SEQ_I);
vga_state.CrtCtrlIndex = inb_p(vga_video_port_reg);
vga_state.CrtMiscIO = vga_r(state->vgabase, VGA_MIS_R);
spin_unlock_irq(&vga_lock);
raw_spin_unlock_irq(&vga_lock);

outb_p(0x00, vga_video_port_reg); /* HorizontalTotal */
vga_state.HorizontalTotal = inb_p(vga_video_port_val);
Expand All @@ -918,7 +918,7 @@ static void vga_vesa_blank(struct vgastate *state, int mode)

/* assure that video is enabled */
/* "0x20" is VIDEO_ENABLE_bit in register 01 of sequencer */
spin_lock_irq(&vga_lock);
raw_spin_lock_irq(&vga_lock);
vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, vga_state.ClockingMode | 0x20);

/* test for vertical retrace in process.... */
Expand Down Expand Up @@ -954,13 +954,13 @@ static void vga_vesa_blank(struct vgastate *state, int mode)
/* restore both index registers */
vga_w(state->vgabase, VGA_SEQ_I, vga_state.SeqCtrlIndex);
outb_p(vga_state.CrtCtrlIndex, vga_video_port_reg);
spin_unlock_irq(&vga_lock);
raw_spin_unlock_irq(&vga_lock);
}

static void vga_vesa_unblank(struct vgastate *state)
{
/* restore original values of VGA controller registers */
spin_lock_irq(&vga_lock);
raw_spin_lock_irq(&vga_lock);
vga_w(state->vgabase, VGA_MIS_W, vga_state.CrtMiscIO);

outb_p(0x00, vga_video_port_reg); /* HorizontalTotal */
Expand All @@ -985,7 +985,7 @@ static void vga_vesa_unblank(struct vgastate *state)
/* restore index/control registers */
vga_w(state->vgabase, VGA_SEQ_I, vga_state.SeqCtrlIndex);
outb_p(vga_state.CrtCtrlIndex, vga_video_port_reg);
spin_unlock_irq(&vga_lock);
raw_spin_unlock_irq(&vga_lock);
}

static void vga_pal_blank(struct vgastate *state)
Expand Down Expand Up @@ -1104,7 +1104,7 @@ static int vgacon_do_font_op(struct vgastate *state,char *arg,int set,int ch512)
charmap += 4 * cmapsz;
#endif

spin_lock_irq(&vga_lock);
raw_spin_lock_irq(&vga_lock);
/* First, the Sequencer */
vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1);
/* CPU writes only to map 2 */
Expand All @@ -1120,7 +1120,7 @@ static int vgacon_do_font_op(struct vgastate *state,char *arg,int set,int ch512)
vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x00);
/* map start at A000:0000 */
vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x00);
spin_unlock_irq(&vga_lock);
raw_spin_unlock_irq(&vga_lock);

if (arg) {
if (set)
Expand All @@ -1147,7 +1147,7 @@ static int vgacon_do_font_op(struct vgastate *state,char *arg,int set,int ch512)
}
}

spin_lock_irq(&vga_lock);
raw_spin_lock_irq(&vga_lock);
/* First, the sequencer, Synchronous reset */
vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x01);
/* CPU writes to maps 0 and 1 */
Expand Down Expand Up @@ -1186,7 +1186,7 @@ static int vgacon_do_font_op(struct vgastate *state,char *arg,int set,int ch512)
inb_p(video_port_status);
vga_wattr(state->vgabase, VGA_AR_ENABLE_DISPLAY, 0);
}
spin_unlock_irq(&vga_lock);
raw_spin_unlock_irq(&vga_lock);
return 0;
}

Expand All @@ -1211,26 +1211,26 @@ static int vgacon_adjust_height(struct vc_data *vc, unsigned fontheight)
registers; they are write-only on EGA, but it appears that they
are all don't care bits on EGA, so I guess it doesn't matter. */

spin_lock_irq(&vga_lock);
raw_spin_lock_irq(&vga_lock);
outb_p(0x07, vga_video_port_reg); /* CRTC overflow register */
ovr = inb_p(vga_video_port_val);
outb_p(0x09, vga_video_port_reg); /* Font size register */
fsr = inb_p(vga_video_port_val);
spin_unlock_irq(&vga_lock);
raw_spin_unlock_irq(&vga_lock);

vde = maxscan & 0xff; /* Vertical display end reg */
ovr = (ovr & 0xbd) + /* Overflow register */
((maxscan & 0x100) >> 7) + ((maxscan & 0x200) >> 3);
fsr = (fsr & 0xe0) + (fontheight - 1); /* Font size register */

spin_lock_irq(&vga_lock);
raw_spin_lock_irq(&vga_lock);
outb_p(0x07, vga_video_port_reg); /* CRTC overflow register */
outb_p(ovr, vga_video_port_val);
outb_p(0x09, vga_video_port_reg); /* Font size */
outb_p(fsr, vga_video_port_val);
outb_p(0x12, vga_video_port_reg); /* Vertical display limit */
outb_p(vde, vga_video_port_val);
spin_unlock_irq(&vga_lock);
raw_spin_unlock_irq(&vga_lock);
vga_video_font_height = fontheight;

for (i = 0; i < MAX_NR_CONSOLES; i++) {
Expand Down

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