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yaml
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r: 31236
b: refs/heads/master
c: 08aecfb
h: refs/heads/master
v: v3
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Yoichi Yuasa authored and Ralf Baechle committed Jun 29, 2006
1 parent 8b48e90 commit bb7e064
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2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: 1500b9a0f4381831e41f7e02f61dbef980ded342
refs/heads/master: 08aecfb9eaf019f07384175101c970ede271c17a
3 changes: 0 additions & 3 deletions trunk/arch/mips/gt64120/wrppmc/irq.c
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Expand Up @@ -62,9 +62,6 @@ void gt64120_init_pic(void)

void __init arch_init_irq(void)
{
/* enable all CPU interrupt bits. */
set_c0_status(ST0_IM); /* IE bit is still 0 */

/* IRQ 0 - 7 are for MIPS common irq_cpu controller */
mips_cpu_irq_init(0);

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