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yaml
---
r: 153854
b: refs/heads/master
c: c416daa
h: refs/heads/master
v: v3
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David Woodhouse authored and David Woodhouse committed May 10, 2009
1 parent b33b2ba commit bc94041
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Showing 4 changed files with 16 additions and 21 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 462b60f6ccc685f7e8aa04ff430e6b4ffedf629f
refs/heads/master: c416daa98a584596df21ee2c26fac6579ee58f57
6 changes: 2 additions & 4 deletions trunk/drivers/pci/dmar.c
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Original file line number Diff line number Diff line change
Expand Up @@ -784,7 +784,6 @@ void dmar_disable_qi(struct intel_iommu *iommu)
cpu_relax();

iommu->gcmd &= ~DMA_GCMD_QIE;

writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);

IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
Expand All @@ -798,7 +797,7 @@ void dmar_disable_qi(struct intel_iommu *iommu)
*/
static void __dmar_enable_qi(struct intel_iommu *iommu)
{
u32 cmd, sts;
u32 sts;
unsigned long flags;
struct q_inval *qi = iommu->qi;

Expand All @@ -812,9 +811,8 @@ static void __dmar_enable_qi(struct intel_iommu *iommu)

dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc));

cmd = iommu->gcmd | DMA_GCMD_QIE;
iommu->gcmd |= DMA_GCMD_QIE;
writel(cmd, iommu->reg + DMAR_GCMD_REG);
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);

/* Make sure hardware complete it */
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
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18 changes: 9 additions & 9 deletions trunk/drivers/pci/intel-iommu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -819,20 +819,19 @@ static int iommu_alloc_root_entry(struct intel_iommu *iommu)
static void iommu_set_root_entry(struct intel_iommu *iommu)
{
void *addr;
u32 cmd, sts;
u32 sts;
unsigned long flag;

addr = iommu->root_entry;

spin_lock_irqsave(&iommu->register_lock, flag);
dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));

cmd = iommu->gcmd | DMA_GCMD_SRTP;
writel(cmd, iommu->reg + DMAR_GCMD_REG);
writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);

/* Make sure hardware complete it */
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
readl, (sts & DMA_GSTS_RTPS), sts);
readl, (sts & DMA_GSTS_RTPS), sts);

spin_unlock_irqrestore(&iommu->register_lock, flag);
}
Expand All @@ -844,12 +843,13 @@ static void iommu_flush_write_buffer(struct intel_iommu *iommu)

if (!rwbf_quirk && !cap_rwbf(iommu->cap))
return;

spin_lock_irqsave(&iommu->register_lock, flag);
writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);

/* Make sure hardware complete it */
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
readl, (!(val & DMA_GSTS_WBFS)), val);
readl, (!(val & DMA_GSTS_WBFS)), val);

spin_unlock_irqrestore(&iommu->register_lock, flag);
}
Expand Down Expand Up @@ -995,13 +995,13 @@ static int iommu_enable_translation(struct intel_iommu *iommu)
unsigned long flags;

spin_lock_irqsave(&iommu->register_lock, flags);
writel(iommu->gcmd|DMA_GCMD_TE, iommu->reg + DMAR_GCMD_REG);
iommu->gcmd |= DMA_GCMD_TE;
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);

/* Make sure hardware complete it */
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
readl, (sts & DMA_GSTS_TES), sts);
readl, (sts & DMA_GSTS_TES), sts);

iommu->gcmd |= DMA_GCMD_TE;
spin_unlock_irqrestore(&iommu->register_lock, flags);
return 0;
}
Expand All @@ -1017,7 +1017,7 @@ static int iommu_disable_translation(struct intel_iommu *iommu)

/* Make sure hardware complete it */
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
readl, (!(sts & DMA_GSTS_TES)), sts);
readl, (!(sts & DMA_GSTS_TES)), sts);

spin_unlock_irqrestore(&iommu->register_lock, flag);
return 0;
Expand Down
11 changes: 4 additions & 7 deletions trunk/drivers/pci/intr_remapping.c
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Original file line number Diff line number Diff line change
Expand Up @@ -404,7 +404,7 @@ int free_irte(int irq)
static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
{
u64 addr;
u32 cmd, sts;
u32 sts;
unsigned long flags;

addr = virt_to_phys((void *)iommu->ir_table->base);
Expand All @@ -415,9 +415,8 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
(addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);

/* Set interrupt-remapping table pointer */
cmd = iommu->gcmd | DMA_GCMD_SIRTP;
iommu->gcmd |= DMA_GCMD_SIRTP;
writel(cmd, iommu->reg + DMAR_GCMD_REG);
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);

IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
readl, (sts & DMA_GSTS_IRTPS), sts);
Expand All @@ -427,9 +426,8 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
spin_lock_irqsave(&iommu->register_lock, flags);

/* enable comaptiblity format interrupt pass through */
cmd = iommu->gcmd | DMA_GCMD_CFI;
iommu->gcmd |= DMA_GCMD_CFI;
writel(cmd, iommu->reg + DMAR_GCMD_REG);
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);

IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
readl, (sts & DMA_GSTS_CFIS), sts);
Expand All @@ -446,9 +444,8 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
spin_lock_irqsave(&iommu->register_lock, flags);

/* Enable interrupt-remapping */
cmd = iommu->gcmd | DMA_GCMD_IRE;
iommu->gcmd |= DMA_GCMD_IRE;
writel(cmd, iommu->reg + DMAR_GCMD_REG);
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);

IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
readl, (sts & DMA_GSTS_IRES), sts);
Expand Down

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