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yaml
---
r: 96837
b: refs/heads/master
c: b3a8b75
h: refs/heads/master
i:
  96835: e013f42
v: v3
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Lennert Buytenhek authored and Russell King committed May 17, 2008
1 parent b7b221d commit bce0c17
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Showing 5 changed files with 5 additions and 5 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: db2c4392907524fa376ffbd04f5781d6394e2666
refs/heads/master: b3a8b751c1c2997653c6bf2b5d10467c39f3cc6e
2 changes: 1 addition & 1 deletion trunk/arch/arm/mm/proc-arm925.S
Original file line number Diff line number Diff line change
Expand Up @@ -332,7 +332,7 @@ ENTRY(arm925_dma_flush_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
#else
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
#endif
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
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2 changes: 1 addition & 1 deletion trunk/arch/arm/mm/proc-arm926.S
Original file line number Diff line number Diff line change
Expand Up @@ -295,7 +295,7 @@ ENTRY(arm926_dma_flush_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
#else
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
#endif
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
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2 changes: 1 addition & 1 deletion trunk/arch/arm/mm/proc-arm940.S
Original file line number Diff line number Diff line change
Expand Up @@ -222,7 +222,7 @@ ENTRY(arm940_dma_flush_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
#else
mcr p15, 0, r3, c7, c10, 2 @ clean D entry
mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
#endif
subs r3, r3, #1 << 26
bcs 2b @ entries 63 to 0
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2 changes: 1 addition & 1 deletion trunk/arch/arm/mm/proc-arm946.S
Original file line number Diff line number Diff line change
Expand Up @@ -265,7 +265,7 @@ ENTRY(arm946_dma_flush_range)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
#else
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
#endif
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
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