Skip to content

Commit

Permalink
Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreq
Browse files Browse the repository at this point in the history 
* master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreq:
  [CPUFREQ] kzalloc conversion for gx-suspmod
  [CPUFREQ] Whitespace cleanup
  [CPUFREQ] Mark longhaul driver as broken.
  [PATCH] cpufreq: fix section mismatch warnings
  [CPUFREQ] Fix the p4-clockmod N60 errata workaround.
  [CPUFREQ] Fix handling for CPU hotplug
  [CPUFREQ] powernow-k8: Let cpufreq driver handle affected CPUs
  [CPUFREQ] Lots of whitespace & CodingStyle cleanup.
  [CPUFREQ] Remove duplicate cpuinfo struct
  [CPUFREQ] Silence powernow-k8 warning on k7's.
  • Loading branch information
Linus Torvalds committed Mar 25, 2006
2 parents ace4847 + 84f0b1e commit be9bf30
Show file tree
Hide file tree
Showing 21 changed files with 414 additions and 404 deletions.
24 changes: 12 additions & 12 deletions arch/i386/kernel/cpu/cpufreq/Kconfig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,6 @@ config X86_POWERNOW_K8_ACPI

config X86_GX_SUSPMOD
tristate "Cyrix MediaGX/NatSemi Geode Suspend Modulation"
depends on PCI
help
This add the CPUFreq driver for NatSemi Geode processors which
support suspend modulation.
Expand All @@ -115,9 +114,9 @@ config X86_SPEEDSTEP_CENTRINO
you also need to say Y to "Use ACPI tables to decode..." below
[which might imply enabling ACPI] if you want to use this driver
on non-Banias CPUs.

For details, take a look at <file:Documentation/cpu-freq/>.

If in doubt, say N.

config X86_SPEEDSTEP_CENTRINO_ACPI
Expand Down Expand Up @@ -148,7 +147,7 @@ config X86_SPEEDSTEP_ICH
help
This adds the CPUFreq driver for certain mobile Intel Pentium III
(Coppermine), all mobile Intel Pentium III-M (Tualatin) and all
mobile Intel Pentium 4 P4-M on systems which have an Intel ICH2,
mobile Intel Pentium 4 P4-M on systems which have an Intel ICH2,
ICH3 or ICH4 southbridge.

For details, take a look at <file:Documentation/cpu-freq/>.
Expand All @@ -161,7 +160,7 @@ config X86_SPEEDSTEP_SMI
depends on EXPERIMENTAL
help
This adds the CPUFreq driver for certain mobile Intel Pentium III
(Coppermine), all mobile Intel Pentium III-M (Tualatin)
(Coppermine), all mobile Intel Pentium III-M (Tualatin)
on systems which have an Intel 440BX/ZX/MX southbridge.

For details, take a look at <file:Documentation/cpu-freq/>.
Expand Down Expand Up @@ -203,9 +202,10 @@ config X86_LONGRUN
config X86_LONGHAUL
tristate "VIA Cyrix III Longhaul"
select CPU_FREQ_TABLE
depends on BROKEN
help
This adds the CPUFreq driver for VIA Samuel/CyrixIII,
VIA Cyrix Samuel/C3, VIA Cyrix Ezra and VIA Cyrix Ezra-T
This adds the CPUFreq driver for VIA Samuel/CyrixIII,
VIA Cyrix Samuel/C3, VIA Cyrix Ezra and VIA Cyrix Ezra-T
processors.

For details, take a look at <file:Documentation/cpu-freq/>.
Expand All @@ -215,11 +215,11 @@ config X86_LONGHAUL
comment "shared options"

config X86_ACPI_CPUFREQ_PROC_INTF
bool "/proc/acpi/processor/../performance interface (deprecated)"
bool "/proc/acpi/processor/../performance interface (deprecated)"
depends on PROC_FS
depends on X86_ACPI_CPUFREQ || X86_SPEEDSTEP_CENTRINO_ACPI || X86_POWERNOW_K7_ACPI || X86_POWERNOW_K8_ACPI
help
This enables the deprecated /proc/acpi/processor/../performance
This enables the deprecated /proc/acpi/processor/../performance
interface. While it is helpful for debugging, the generic,
cross-architecture cpufreq interfaces should be used.

Expand All @@ -233,9 +233,9 @@ config X86_SPEEDSTEP_RELAXED_CAP_CHECK
bool "Relaxed speedstep capability checks"
depends on (X86_SPEEDSTEP_SMI || X86_SPEEDSTEP_ICH)
help
Don't perform all checks for a speedstep capable system which would
normally be done. Some ancient or strange systems, though speedstep
capable, don't always indicate that they are speedstep capable. This
Don't perform all checks for a speedstep capable system which would
normally be done. Some ancient or strange systems, though speedstep
capable, don't always indicate that they are speedstep capable. This
option lets the probing code bypass some of those checks if the
parameter "relaxed_check=1" is passed to the module.

Expand Down
64 changes: 26 additions & 38 deletions arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ static struct pci_dev *nforce2_chipset_dev;
static int fid = 0;

/* min_fsb, max_fsb:
* minimum and maximum FSB (= FSB at boot time)
* minimum and maximum FSB (= FSB at boot time)
*/
static int min_fsb = 0;
static int max_fsb = 0;
Expand All @@ -57,10 +57,10 @@ MODULE_PARM_DESC(min_fsb,

#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-nforce2", msg)

/*
/**
* nforce2_calc_fsb - calculate FSB
* @pll: PLL value
*
*
* Calculates FSB from PLL value
*/
static int nforce2_calc_fsb(int pll)
Expand All @@ -76,10 +76,10 @@ static int nforce2_calc_fsb(int pll)
return 0;
}

/*
/**
* nforce2_calc_pll - calculate PLL value
* @fsb: FSB
*
*
* Calculate PLL value for given FSB
*/
static int nforce2_calc_pll(unsigned int fsb)
Expand All @@ -106,10 +106,10 @@ static int nforce2_calc_pll(unsigned int fsb)
return NFORCE2_PLL(mul, div);
}

/*
/**
* nforce2_write_pll - write PLL value to chipset
* @pll: PLL value
*
*
* Writes new FSB PLL value to chipset
*/
static void nforce2_write_pll(int pll)
Expand All @@ -121,15 +121,13 @@ static void nforce2_write_pll(int pll)
pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp);

/* Now write the value in all 64 registers */
for (temp = 0; temp <= 0x3f; temp++) {
pci_write_config_dword(nforce2_chipset_dev,
NFORCE2_PLLREG, pll);
}
for (temp = 0; temp <= 0x3f; temp++)
pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLREG, pll);

return;
}

/*
/**
* nforce2_fsb_read - Read FSB
*
* Read FSB from chipset
Expand All @@ -140,39 +138,32 @@ static unsigned int nforce2_fsb_read(int bootfsb)
struct pci_dev *nforce2_sub5;
u32 fsb, temp = 0;


/* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
0x01EF,
PCI_ANY_ID,
PCI_ANY_ID,
NULL);

0x01EF,PCI_ANY_ID,PCI_ANY_ID,NULL);
if (!nforce2_sub5)
return 0;

pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
fsb /= 1000000;

/* Check if PLL register is already set */
pci_read_config_byte(nforce2_chipset_dev,
NFORCE2_PLLENABLE, (u8 *)&temp);

pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);

if(bootfsb || !temp)
return fsb;

/* Use PLL register FSB value */
pci_read_config_dword(nforce2_chipset_dev,
NFORCE2_PLLREG, &temp);
pci_read_config_dword(nforce2_chipset_dev,NFORCE2_PLLREG, &temp);
fsb = nforce2_calc_fsb(temp);

return fsb;
}

/*
/**
* nforce2_set_fsb - set new FSB
* @fsb: New FSB
*
*
* Sets new FSB
*/
static int nforce2_set_fsb(unsigned int fsb)
Expand All @@ -186,16 +177,15 @@ static int nforce2_set_fsb(unsigned int fsb)
printk(KERN_ERR "cpufreq: FSB %d is out of range!\n", fsb);
return -EINVAL;
}

tfsb = nforce2_fsb_read(0);
if (!tfsb) {
printk(KERN_ERR "cpufreq: Error while reading the FSB\n");
return -EINVAL;
}

/* First write? Then set actual value */
pci_read_config_byte(nforce2_chipset_dev,
NFORCE2_PLLENABLE, (u8 *)&temp);
pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
if (!temp) {
pll = nforce2_calc_pll(tfsb);

Expand Down Expand Up @@ -223,7 +213,7 @@ static int nforce2_set_fsb(unsigned int fsb)
/* Calculate the PLL reg. value */
if ((pll = nforce2_calc_pll(tfsb)) == -1)
return -EINVAL;

nforce2_write_pll(pll);
#ifdef NFORCE2_DELAY
mdelay(NFORCE2_DELAY);
Expand All @@ -239,7 +229,7 @@ static int nforce2_set_fsb(unsigned int fsb)
/**
* nforce2_get - get the CPU frequency
* @cpu: CPU number
*
*
* Returns the CPU frequency
*/
static unsigned int nforce2_get(unsigned int cpu)
Expand Down Expand Up @@ -354,10 +344,10 @@ static int nforce2_cpu_init(struct cpufreq_policy *policy)

printk(KERN_INFO "cpufreq: FSB currently at %i MHz, FID %d.%d\n", fsb,
fid / 10, fid % 10);

/* Set maximum FSB to FSB at boot time */
max_fsb = nforce2_fsb_read(1);

if(!max_fsb)
return -EIO;

Expand Down Expand Up @@ -398,17 +388,15 @@ static struct cpufreq_driver nforce2_driver = {
* nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
*
* Detects nForce2 A2 and C1 stepping
*
*
*/
static unsigned int nforce2_detect_chipset(void)
{
u8 revision;

nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_NFORCE2,
PCI_ANY_ID,
PCI_ANY_ID,
NULL);
PCI_DEVICE_ID_NVIDIA_NFORCE2,
PCI_ANY_ID, PCI_ANY_ID, NULL);

if (nforce2_chipset_dev == NULL)
return -ENODEV;
Expand Down
Loading

0 comments on commit be9bf30

Please sign in to comment.