---

yaml
---
r: 91198
b: refs/heads/master
c: 98f79d1
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 5d4294c524fc53746b5ec138d2e90f9d34d754b0
+refs/heads/master: 98f79d1ea0459b907f95846bad5e967a06b7a0d5

trunk/arch/arm/mach-orion/addr-map.c

@@ -25,10 +25,10 @@
  * CPU address decoding --
  * Linux assumes that it is the boot loader that already setup the access to
  * DDR and internal registers.
- * Setup access to PCI and PCI-E IO/MEM space is issued by core.c.
+ * Setup access to PCI and PCI-E IO/MEM space is issued by this file.
  * Setup access to various devices located on the device bus interface (e.g.
  * flashes, RTC, etc) should be issued by machine-setup.c according to
- * specific board population (by using orion_setup_cpu_win()).
+ * specific board population (by using orion_setup_*_win()).
  *
  * Non-CPU Masters address decoding --
  * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
@@ -53,6 +53,7 @@
 				((n) == 3) ? 0x7 : 0xf)
 #define ATTR_PCIE_MEM		0x59
 #define ATTR_PCIE_IO		0x51
+#define ATTR_PCIE_WA		0x79
 #define ATTR_PCI_MEM		0x59
 #define ATTR_PCI_IO		0x51
 #define ATTR_DEV_CS0		0x1e
@@ -78,19 +79,6 @@
 #define CPU_WIN_BASE(n)		ORION_BRIDGE_REG(0x004 | ((n) << 4))
 #define CPU_WIN_REMAP_LO(n)	ORION_BRIDGE_REG(0x008 | ((n) << 4))
 #define CPU_WIN_REMAP_HI(n)	ORION_BRIDGE_REG(0x00c | ((n) << 4))
-#define CPU_MAX_WIN		8
-
-/*
- * Use this CPU address decode windows allocation
- */
-#define CPU_WIN_PCIE_IO		0
-#define CPU_WIN_PCI_IO		1
-#define CPU_WIN_PCIE_MEM	2
-#define CPU_WIN_PCI_MEM		3
-#define CPU_WIN_DEV_BOOT	4
-#define CPU_WIN_DEV_CS0		5
-#define CPU_WIN_DEV_CS1		6
-#define CPU_WIN_DEV_CS2		7
 
 /*
  * Gigabit Ethernet Address Decode Windows registers
@@ -106,7 +94,7 @@
 
 struct mbus_dram_target_info orion_mbus_dram_info;
 
-static int __init orion_cpu_win_can_remap(u32 win)
+static int __init orion_cpu_win_can_remap(int win)
 {
 	u32 dev, rev;
 
@@ -119,88 +107,31 @@ static int __init orion_cpu_win_can_remap(u32 win)
 	return 0;
 }
 
-void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap)
+static void __init setup_cpu_win(int win, u32 base, u32 size,
+				 u8 target, u8 attr, int remap)
 {
-	u32 win, attr, ctrl;
-
-	switch (target) {
-	case ORION_PCIE_IO:
-		target = TARGET_PCIE;
-		attr = ATTR_PCIE_IO;
-		win = CPU_WIN_PCIE_IO;
-		break;
-	case ORION_PCI_IO:
-		target = TARGET_PCI;
-		attr = ATTR_PCI_IO;
-		win = CPU_WIN_PCI_IO;
-		break;
-	case ORION_PCIE_MEM:
-		target = TARGET_PCIE;
-		attr = ATTR_PCIE_MEM;
-		win = CPU_WIN_PCIE_MEM;
-		break;
-	case ORION_PCI_MEM:
-		target = TARGET_PCI;
-		attr = ATTR_PCI_MEM;
-		win = CPU_WIN_PCI_MEM;
-		break;
-	case ORION_DEV_BOOT:
-		target = TARGET_DEV_BUS;
-		attr = ATTR_DEV_BOOT;
-		win = CPU_WIN_DEV_BOOT;
-		break;
-	case ORION_DEV0:
-		target = TARGET_DEV_BUS;
-		attr = ATTR_DEV_CS0;
-		win = CPU_WIN_DEV_CS0;
-		break;
-	case ORION_DEV1:
-		target = TARGET_DEV_BUS;
-		attr = ATTR_DEV_CS1;
-		win = CPU_WIN_DEV_CS1;
-		break;
-	case ORION_DEV2:
-		target = TARGET_DEV_BUS;
-		attr = ATTR_DEV_CS2;
-		win = CPU_WIN_DEV_CS2;
-		break;
-	case ORION_DDR:
-	case ORION_REGS:
-		/*
-		 * Must be mapped by bootloader.
-		 */
-	default:
-		target = attr = win = -1;
-		BUG();
-	}
-
-	base &= 0xffff0000;
-	ctrl = (((size - 1) & 0xffff0000) | (attr << 8) |
-		(target << 4) | WIN_EN);
-
-	orion_write(CPU_WIN_BASE(win), base);
-	orion_write(CPU_WIN_CTRL(win), ctrl);
+	orion_write(CPU_WIN_BASE(win), base & 0xffff0000);
+	orion_write(CPU_WIN_CTRL(win),
+		((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1);
 
 	if (orion_cpu_win_can_remap(win)) {
-		if (remap >= 0) {
-			orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
-			orion_write(CPU_WIN_REMAP_HI(win), 0);
-		} else {
-			orion_write(CPU_WIN_REMAP_LO(win), base);
-			orion_write(CPU_WIN_REMAP_HI(win), 0);
-		}
+		if (remap < 0)
+			remap = base;
+
+		orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
+		orion_write(CPU_WIN_REMAP_HI(win), 0);
 	}
 }
 
-void __init orion_setup_cpu_wins(void)
+void __init orion_setup_cpu_mbus_bridge(void)
 {
 	int i;
 	int cs;
 
 	/*
-	 * First, disable and clear windows
+	 * First, disable and clear windows.
 	 */
-	for (i = 0; i < CPU_MAX_WIN; i++) {
+	for (i = 0; i < 8; i++) {
 		orion_write(CPU_WIN_BASE(i), 0);
 		orion_write(CPU_WIN_CTRL(i), 0);
 		if (orion_cpu_win_can_remap(i)) {
@@ -212,14 +143,14 @@ void __init orion_setup_cpu_wins(void)
 	/*
 	 * Setup windows for PCI+PCIe IO+MEM space.
 	 */
-	orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE,
-				ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE);
-	orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE,
-				ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE);
-	orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE,
-				ORION_PCIE_MEM_SIZE, -1);
-	orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
-				ORION_PCI_MEM_SIZE, -1);
+	setup_cpu_win(0, ORION_PCIE_IO_PHYS_BASE, ORION_PCIE_IO_SIZE,
+		TARGET_PCIE, ATTR_PCIE_IO, ORION_PCIE_IO_BUS_BASE);
+	setup_cpu_win(1, ORION_PCI_IO_PHYS_BASE, ORION_PCI_IO_SIZE,
+		TARGET_PCI, ATTR_PCI_IO, ORION_PCI_IO_BUS_BASE);
+	setup_cpu_win(2, ORION_PCIE_MEM_PHYS_BASE, ORION_PCIE_MEM_SIZE,
+		TARGET_PCIE, ATTR_PCIE_MEM, -1);
+	setup_cpu_win(3, ORION_PCI_MEM_PHYS_BASE, ORION_PCI_MEM_SIZE,
+		TARGET_PCI, ATTR_PCI_MEM, -1);
 
 	/*
 	 * Setup MBUS dram target info.
@@ -246,6 +177,31 @@ void __init orion_setup_cpu_wins(void)
 	orion_mbus_dram_info.num_cs = cs;
 }
 
+void __init orion_setup_dev_boot_win(u32 base, u32 size)
+{
+	setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
+}
+
+void __init orion_setup_dev0_win(u32 base, u32 size)
+{
+	setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
+}
+
+void __init orion_setup_dev1_win(u32 base, u32 size)
+{
+	setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
+}
+
+void __init orion_setup_dev2_win(u32 base, u32 size)
+{
+	setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
+}
+
+void __init orion_setup_pcie_wa_win(u32 base, u32 size)
+{
+	setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
+}
+
 void __init orion_setup_eth_wins(void)
 {
 	int i;

trunk/arch/arm/mach-orion/common.c

@@ -359,7 +359,7 @@ void __init orion_init(void)
 	/*
 	 * Setup Orion address map
 	 */
-	orion_setup_cpu_wins();
+	orion_setup_cpu_mbus_bridge();
 	orion_setup_eth_wins();
 
 	/*

trunk/arch/arm/mach-orion/common.h

@@ -15,24 +15,13 @@ extern struct sys_timer orion_timer;
  * functions to map its interfaces and by the machine-setup to map its on-
  * board devices. Details in /mach-orion/addr-map.c
  */
-
-enum orion_target {
-	ORION_DEV_BOOT = 0,
-	ORION_DEV0,
-	ORION_DEV1,
-	ORION_DEV2,
-	ORION_PCIE_MEM,
-	ORION_PCIE_IO,
-	ORION_PCI_MEM,
-	ORION_PCI_IO,
-	ORION_DDR,
-	ORION_REGS,
-	ORION_MAX_TARGETS
-};
-
 extern struct mbus_dram_target_info orion_mbus_dram_info;
-void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap);
-void orion_setup_cpu_wins(void);
+void orion_setup_cpu_mbus_bridge(void);
+void orion_setup_dev_boot_win(u32 base, u32 size);
+void orion_setup_dev0_win(u32 base, u32 size);
+void orion_setup_dev1_win(u32 base, u32 size);
+void orion_setup_dev2_win(u32 base, u32 size);
+void orion_setup_pcie_wa_win(u32 base, u32 size);
 void orion_setup_eth_wins(void);
 
 /*

trunk/arch/arm/mach-orion/db88f5281-setup.c

@@ -317,14 +317,11 @@ static void __init db88f5281_init(void)
 	/*
 	 * Setup the CPU address decode windows for our on-board devices
 	 */
-	orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE,
-				DB88F5281_NOR_BOOT_SIZE, -1);
-	orion_setup_cpu_win(ORION_DEV0,	DB88F5281_7SEG_BASE,
-				DB88F5281_7SEG_SIZE, -1);
-	orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE,
-				DB88F5281_NOR_SIZE, -1);
-	orion_setup_cpu_win(ORION_DEV2,	DB88F5281_NAND_BASE,
-				DB88F5281_NAND_SIZE, -1);
+	orion_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
+				DB88F5281_NOR_BOOT_SIZE);
+	orion_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
+	orion_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
+	orion_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
 
 	/*
 	 * Setup Multiplexing Pins:

trunk/arch/arm/mach-orion/dns323-setup.c

@@ -251,16 +251,13 @@ static void __init dns323_init(void)
 	/* setup flash mapping
 	 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
 	 */
-	orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE,
-			    DNS323_NOR_BOOT_SIZE, -1);
+	orion_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
 
 	/* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE
 	 *
 	 * Open a special address decode windows for the PCIE WA.
 	 */
-	orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
-	orion_write(ORION_REGS_VIRT_BASE | 0x20070,
-		    (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+	orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE);
 
 	/* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
 	orion_write(MPP_0_7_CTRL, 0);

trunk/arch/arm/mach-orion/kurobox_pro-setup.c

@@ -193,16 +193,14 @@ static void __init kurobox_pro_init(void)
 	/*
 	 * Setup the CPU address decode windows for our devices
 	 */
-	orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE,
-				KUROBOX_PRO_NOR_BOOT_SIZE, -1);
-	orion_setup_cpu_win(ORION_DEV0,	KUROBOX_PRO_NAND_BASE,
-				KUROBOX_PRO_NAND_SIZE, -1);
+	orion_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
+				KUROBOX_PRO_NOR_BOOT_SIZE);
+	orion_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE);
+
 	/*
 	 * Open a special address decode windows for the PCIE WA.
 	 */
-	orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
-	orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
-		(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+	orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE);
 
 	/*
 	 * Setup Multiplexing Pins --

trunk/arch/arm/mach-orion/rd88f5182-setup.c

@@ -254,17 +254,14 @@ static void __init rd88f5182_init(void)
 	/*
 	 * Setup the CPU address decode windows for our devices
 	 */
-	orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE,
-				RD88F5182_NOR_BOOT_SIZE, -1);
-	orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE,
-				RD88F5182_NOR_SIZE, -1);
+	orion_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
+				RD88F5182_NOR_BOOT_SIZE);
+	orion_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
 
 	/*
 	 * Open a special address decode windows for the PCIE WA.
 	 */
-	orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
-	orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
-		(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+	orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE);
 
 	/*
 	 * Setup Multiplexing Pins --

trunk/arch/arm/mach-orion/ts209-setup.c

@@ -288,15 +288,13 @@ static void __init qnap_ts209_init(void)
 	/*
 	 * Setup flash mapping
 	 */
-	orion_setup_cpu_win(ORION_DEV_BOOT, QNAP_TS209_NOR_BOOT_BASE,
-			    QNAP_TS209_NOR_BOOT_SIZE, -1);
+	orion_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
+			    QNAP_TS209_NOR_BOOT_SIZE);
 
 	/*
 	 * Open a special address decode windows for the PCIE WA.
 	 */
-	orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
-	orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
-		(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+	orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE);
 
 	/*
 	 * Setup Multiplexing Pins --