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[POWERPC] 85xx: Add next-level-cache property
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Added next-level-cache to the L1 and a reference to the new L2 label.
This is per the ePAPR 0.94 spec.  Since we are't really dependent on this
today we aren't supporting the "legacy" l2-cache phandle that is specified
in the PPC v2.1 OF Binding spec.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala committed Jun 2, 2008
1 parent acd4b71 commit c054065
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Showing 16 changed files with 32 additions and 16 deletions.
3 changes: 2 additions & 1 deletion arch/powerpc/boot/dts/ksi8560.dts
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Expand Up @@ -40,6 +40,7 @@
timebase-frequency = <0>; /* From U-boot */
bus-frequency = <0>; /* From U-boot */
clock-frequency = <0>; /* From U-boot */
next-level-cache = <&L2>;
};
};

Expand All @@ -62,7 +63,7 @@
interrupts = <0x12 0x2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <0x20>; /* 32 bytes */
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3 changes: 2 additions & 1 deletion arch/powerpc/boot/dts/mpc8540ads.dts
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Expand Up @@ -40,6 +40,7 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
next-level-cache = <&L2>;
};
};

Expand All @@ -63,7 +64,7 @@
interrupts = <18 2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
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3 changes: 2 additions & 1 deletion arch/powerpc/boot/dts/mpc8541cds.dts
Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
next-level-cache = <&L2>;
};
};

Expand All @@ -63,7 +64,7 @@
interrupts = <18 2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8541-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
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3 changes: 2 additions & 1 deletion arch/powerpc/boot/dts/mpc8544ds.dts
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,7 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};

Expand All @@ -65,7 +66,7 @@
interrupts = <18 2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8544-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
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3 changes: 2 additions & 1 deletion arch/powerpc/boot/dts/mpc8548cds.dts
Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,7 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
next-level-cache = <&L2>;
};
};

Expand All @@ -68,7 +69,7 @@
interrupts = <18 2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
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3 changes: 2 additions & 1 deletion arch/powerpc/boot/dts/mpc8555cds.dts
Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
next-level-cache = <&L2>;
};
};

Expand All @@ -63,7 +64,7 @@
interrupts = <18 2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8555-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
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2 changes: 1 addition & 1 deletion arch/powerpc/boot/dts/mpc8560ads.dts
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@
interrupts = <18 2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
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3 changes: 2 additions & 1 deletion arch/powerpc/boot/dts/mpc8568mds.dts
Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,7 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};

Expand Down Expand Up @@ -70,7 +71,7 @@
interrupts = <18 2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8568-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
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4 changes: 3 additions & 1 deletion arch/powerpc/boot/dts/mpc8572ds.dts
Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,7 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};

PowerPC,8572@1 {
Expand All @@ -54,6 +55,7 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};

Expand Down Expand Up @@ -84,7 +86,7 @@
interrupts = <18 2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8572-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
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3 changes: 2 additions & 1 deletion arch/powerpc/boot/dts/sbc8548.dts
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,7 @@
timebase-frequency = <0>; // From uboot
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};

Expand Down Expand Up @@ -161,7 +162,7 @@
interrupts = <0x12 0x2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <0x20>; // 32 bytes
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3 changes: 2 additions & 1 deletion arch/powerpc/boot/dts/sbc8560.dts
Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,7 @@
timebase-frequency = <0>; // From uboot
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};

Expand All @@ -66,7 +67,7 @@
interrupts = <0x12 0x2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8560-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <0x20>; // 32 bytes
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3 changes: 2 additions & 1 deletion arch/powerpc/boot/dts/stx_gp3_8560.dts
Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,7 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};

Expand All @@ -62,7 +63,7 @@
interrupts = <18 2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;
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3 changes: 2 additions & 1 deletion arch/powerpc/boot/dts/tqm8540.dts
Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};

Expand All @@ -64,7 +65,7 @@
interrupts = <18 2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;
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3 changes: 2 additions & 1 deletion arch/powerpc/boot/dts/tqm8541.dts
Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,7 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};

Expand All @@ -63,7 +64,7 @@
interrupts = <18 2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;
Expand Down
3 changes: 2 additions & 1 deletion arch/powerpc/boot/dts/tqm8555.dts
Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,7 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};

Expand All @@ -63,7 +64,7 @@
interrupts = <18 2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;
Expand Down
3 changes: 2 additions & 1 deletion arch/powerpc/boot/dts/tqm8560.dts
Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};

Expand All @@ -64,7 +65,7 @@
interrupts = <18 2>;
};

l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;
Expand Down

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