---

yaml
---
r: 56687
b: refs/heads/master
c: 0f347bb
h: refs/heads/master
i:
  56685: 626af77
  56683: 985bd32
  56679: f947dbe
  56671: 12a3856
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: f3270f6ef7d60251617f9d4c08f76ec01c647aa4
+refs/heads/master: 0f347bb9136f55ff575d55441a29e92c16e87fb0

trunk/arch/arm/common/gic.c

@@ -125,12 +125,11 @@ static void gic_set_cpu(unsigned int irq, cpumask_t mask_val)
 }
 #endif
 
-static void fastcall gic_handle_cascade_irq(unsigned int irq,
-					    struct irq_desc *desc)
+static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 {
 	struct gic_chip_data *chip_data = get_irq_data(irq);
 	struct irq_chip *chip = get_irq_chip(irq);
-	unsigned int cascade_irq;
+	unsigned int cascade_irq, gic_irq;
 	unsigned long status;
 
 	/* primary controller ack'ing */
@@ -140,16 +139,15 @@ static void fastcall gic_handle_cascade_irq(unsigned int irq,
 	status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
 	spin_unlock(&irq_controller_lock);
 
-	cascade_irq = (status & 0x3ff);
-	if (cascade_irq > 1020)
+	gic_irq = (status & 0x3ff);
+	if (gic_irq == 1023)
 		goto out;
-	if (cascade_irq < 32 || cascade_irq >= NR_IRQS) {
-		do_bad_IRQ(cascade_irq, desc);
-		goto out;
-	}
 
-	cascade_irq += chip_data->irq_offset;
-	generic_handle_irq(cascade_irq);
+	cascade_irq = gic_irq + chip_data->irq_offset;
+	if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
+		do_bad_IRQ(cascade_irq, desc);
+	else
+		generic_handle_irq(cascade_irq);
 
  out:
 	/* primary controller unmasking */