---

yaml
---
r: 24578
b: refs/heads/master
c: e2f8165
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 147830f297f369fa8731a75e3e4c7c7cd5c3e868
+refs/heads/master: e2f8165dc3c70cd74bcf2c63a6c0de254c6ff50c

trunk/drivers/ieee1394/ohci1394.c

@@ -572,6 +572,7 @@ static void ohci_initialize(struct ti_ohci *ohci)
 		  OHCI1394_reqTxComplete |
 		  OHCI1394_isochRx |
 		  OHCI1394_isochTx |
+		  OHCI1394_postedWriteErr |
 		  OHCI1394_cycleInconsistent);
 
 	/* Enable link */
@@ -2374,15 +2375,17 @@ static irqreturn_t ohci_irq_handler(int irq, void *dev_id,
 
 		event &= ~OHCI1394_unrecoverableError;
 	}
-
+	if (event & OHCI1394_postedWriteErr) {
+		PRINT(KERN_ERR, "physical posted write error");
+		/* no recovery strategy yet, had to involve protocol drivers */
+	}
 	if (event & OHCI1394_cycleInconsistent) {
 		/* We subscribe to the cycleInconsistent event only to
 		 * clear the corresponding event bit... otherwise,
 		 * isochronous cycleMatch DMA won't work. */
 		DBGMSG("OHCI1394_cycleInconsistent");
 		event &= ~OHCI1394_cycleInconsistent;
 	}
-
 	if (event & OHCI1394_busReset) {
 		/* The busReset event bit can't be cleared during the
 		 * selfID phase, so we disable busReset interrupts, to
@@ -2426,7 +2429,6 @@ static irqreturn_t ohci_irq_handler(int irq, void *dev_id,
 		}
 		event &= ~OHCI1394_busReset;
 	}
-
 	if (event & OHCI1394_reqTxComplete) {
 		struct dma_trm_ctx *d = &ohci->at_req_context;
 		DBGMSG("Got reqTxComplete interrupt "