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r: 199794
b: refs/heads/master
c: bc23416
h: refs/heads/master
v: v3
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Linus Torvalds committed Jun 4, 2010
1 parent 0ad5da4 commit c1aa267
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2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: d4376802999d478a103868d7e7b1f473e4a387af
refs/heads/master: bc23416cd4579093acc1e7d819eee747def623da
12 changes: 6 additions & 6 deletions trunk/Documentation/DocBook/drm.tmpl
Original file line number Diff line number Diff line change
Expand Up @@ -389,7 +389,7 @@
</para>
<para>
If your driver supports memory management (it should!), you'll
need to set that up at load time as well. How you intialize
need to set that up at load time as well. How you initialize
it depends on which memory manager you're using, TTM or GEM.
</para>
<sect3>
Expand All @@ -399,7 +399,7 @@
aperture space for graphics devices. TTM supports both UMA devices
and devices with dedicated video RAM (VRAM), i.e. most discrete
graphics devices. If your device has dedicated RAM, supporting
TTM is desireable. TTM also integrates tightly with your
TTM is desirable. TTM also integrates tightly with your
driver specific buffer execution function. See the radeon
driver for examples.
</para>
Expand Down Expand Up @@ -443,7 +443,7 @@
likely eventually calling ttm_bo_global_init and
ttm_bo_global_release, respectively. Also like the previous
object, ttm_global_item_ref is used to create an initial reference
count for the TTM, which will call your initalization function.
count for the TTM, which will call your initialization function.
</para>
</sect3>
<sect3>
Expand Down Expand Up @@ -557,7 +557,7 @@ void intel_crt_init(struct drm_device *dev)
CRT connector and encoder combination is created. A device
specific i2c bus is also created, for fetching EDID data and
performing monitor detection. Once the process is complete,
the new connector is regsitered with sysfs, to make its
the new connector is registered with sysfs, to make its
properties available to applications.
</para>
<sect4>
Expand All @@ -581,12 +581,12 @@ void intel_crt_init(struct drm_device *dev)
<para>
For each encoder, CRTC and connector, several functions must
be provided, depending on the object type. Encoder objects
need should provide a DPMS (basically on/off) function, mode fixup
need to provide a DPMS (basically on/off) function, mode fixup
(for converting requested modes into native hardware timings),
and prepare, set and commit functions for use by the core DRM
helper functions. Connector helpers need to provide mode fetch and
validity functions as well as an encoder matching function for
returing an ideal encoder for a given connector. The core
returning an ideal encoder for a given connector. The core
connector functions include a DPMS callback, (deprecated)
save/restore routines, detection, mode probing, property handling,
and cleanup functions.
Expand Down
4 changes: 2 additions & 2 deletions trunk/Documentation/i2c/busses/i2c-ali1535
Original file line number Diff line number Diff line change
Expand Up @@ -6,12 +6,12 @@ Supported adapters:
http://www.ali.com.tw/eng/support/datasheet_request.php

Authors:
Frodo Looijaard <frodol@dds.nl>,
Frodo Looijaard <frodol@dds.nl>,
Philip Edelbrock <phil@netroedge.com>,
Mark D. Studebaker <mdsxyz123@yahoo.com>,
Dan Eaton <dan.eaton@rocketlogix.com>,
Stephen Rousset<stephen.rousset@rocketlogix.com>

Description
-----------

Expand Down
2 changes: 1 addition & 1 deletion trunk/Documentation/i2c/busses/i2c-ali1563
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ For an overview of these chips see http://www.acerlabs.com
The M1563 southbridge is deceptively similar to the M1533, with a few
notable exceptions. One of those happens to be the fact they upgraded the
i2c core to be SMBus 2.0 compliant, and happens to be almost identical to
the i2c controller found in the Intel 801 south bridges.
the i2c controller found in the Intel 801 south bridges.

Features
--------
Expand Down
16 changes: 8 additions & 8 deletions trunk/Documentation/i2c/busses/i2c-ali15x3
Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,8 @@ Supported adapters:
http://www.ali.com.tw/eng/support/datasheet_request.php

Authors:
Frodo Looijaard <frodol@dds.nl>,
Philip Edelbrock <phil@netroedge.com>,
Frodo Looijaard <frodol@dds.nl>,
Philip Edelbrock <phil@netroedge.com>,
Mark D. Studebaker <mdsxyz123@yahoo.com>

Module Parameters
Expand Down Expand Up @@ -40,10 +40,10 @@ M1541 and M1543C South Bridges.
The M1543C is a South bridge for desktop systems.
The M1541 is a South bridge for portable systems.
They are part of the following ALI chipsets:
* "Aladdin Pro 2" includes the M1621 Slot 1 North bridge with AGP and

* "Aladdin Pro 2" includes the M1621 Slot 1 North bridge with AGP and
100MHz CPU Front Side bus
* "Aladdin V" includes the M1541 Socket 7 North bridge with AGP and 100MHz
* "Aladdin V" includes the M1541 Socket 7 North bridge with AGP and 100MHz
CPU Front Side bus
Some Aladdin V motherboards:
Asus P5A
Expand Down Expand Up @@ -77,7 +77,7 @@ output of lspci will show something similar to the following:
** then run lspci.
** If you see the 1533 and 5229 devices but NOT the 7101 device,
** then you must enable ACPI, the PMU, SMB, or something similar
** in the BIOS.
** in the BIOS.
** The driver won't work if it can't find the M7101 device.

The SMB controller is part of the M7101 device, which is an ACPI-compliant
Expand All @@ -87,8 +87,8 @@ The whole M7101 device has to be enabled for the SMB to work. You can't
just enable the SMB alone. The SMB and the ACPI have separate I/O spaces.
We make sure that the SMB is enabled. We leave the ACPI alone.

Features
--------
Features
--------

This driver controls the SMB Host only. The SMB Slave
controller on the M15X3 is not enabled. This driver does not use
Expand Down
14 changes: 7 additions & 7 deletions trunk/Documentation/i2c/busses/i2c-pca-isa
Original file line number Diff line number Diff line change
@@ -1,23 +1,23 @@
Kernel driver i2c-pca-isa

Supported adapters:
This driver supports ISA boards using the Philips PCA 9564
Parallel bus to I2C bus controller
This driver supports ISA boards using the Philips PCA 9564
Parallel bus to I2C bus controller

Author: Ian Campbell <icampbell@arcom.com>, Arcom Control Systems
Author: Ian Campbell <icampbell@arcom.com>, Arcom Control Systems

Module Parameters
-----------------

* base int
I/O base address
* irq int
IRQ interrupt
* clock int
IRQ interrupt
* clock int
Clock rate as described in table 1 of PCA9564 datasheet

Description
-----------

This driver supports ISA boards using the Philips PCA 9564
Parallel bus to I2C bus controller
This driver supports ISA boards using the Philips PCA 9564
Parallel bus to I2C bus controller
58 changes: 29 additions & 29 deletions trunk/Documentation/i2c/busses/i2c-sis5595
Original file line number Diff line number Diff line change
@@ -1,41 +1,41 @@
Kernel driver i2c-sis5595

Authors:
Authors:
Frodo Looijaard <frodol@dds.nl>,
Mark D. Studebaker <mdsxyz123@yahoo.com>,
Philip Edelbrock <phil@netroedge.com>
Philip Edelbrock <phil@netroedge.com>

Supported adapters:
* Silicon Integrated Systems Corp. SiS5595 Southbridge
Datasheet: Publicly available at the Silicon Integrated Systems Corp. site.

Note: all have mfr. ID 0x1039.

SUPPORTED PCI ID
5595 0008
Note: these chips contain a 0008 device which is incompatible with the
5595. We recognize these by the presence of the listed
"blacklist" PCI ID and refuse to load.
NOT SUPPORTED PCI ID BLACKLIST PCI ID
540 0008 0540
550 0008 0550
5513 0008 5511
5581 0008 5597
5582 0008 5597
5597 0008 5597
5598 0008 5597/5598
630 0008 0630
645 0008 0645
646 0008 0646
648 0008 0648
650 0008 0650
651 0008 0651
730 0008 0730
735 0008 0735
745 0008 0745
746 0008 0746
Note: all have mfr. ID 0x1039.

SUPPORTED PCI ID
5595 0008

Note: these chips contain a 0008 device which is incompatible with the
5595. We recognize these by the presence of the listed
"blacklist" PCI ID and refuse to load.

NOT SUPPORTED PCI ID BLACKLIST PCI ID
540 0008 0540
550 0008 0550
5513 0008 5511
5581 0008 5597
5582 0008 5597
5597 0008 5597
5598 0008 5597/5598
630 0008 0630
645 0008 0645
646 0008 0646
648 0008 0648
650 0008 0650
651 0008 0651
730 0008 0730
735 0008 0735
745 0008 0745
746 0008 0746

Module Parameters
-----------------
Expand Down
8 changes: 4 additions & 4 deletions trunk/Documentation/i2c/busses/i2c-sis630
Original file line number Diff line number Diff line change
Expand Up @@ -14,9 +14,9 @@ Module Parameters
* force = [1|0] Forcibly enable the SIS630. DANGEROUS!
This can be interesting for chipsets not named
above to check if it works for you chipset, but DANGEROUS!
* high_clock = [1|0] Forcibly set Host Master Clock to 56KHz (default,
what your BIOS use). DANGEROUS! This should be a bit

* high_clock = [1|0] Forcibly set Host Master Clock to 56KHz (default,
what your BIOS use). DANGEROUS! This should be a bit
faster, but freeze some systems (i.e. my Laptop).


Expand Down Expand Up @@ -44,6 +44,6 @@ Philip Edelbrock <phil@netroedge.com>
- testing SiS730 support
Mark M. Hoffman <mhoffman@lightlink.com>
- bug fixes

To anyone else which I forgot here ;), thanks!

6 changes: 3 additions & 3 deletions trunk/Documentation/i2c/ten-bit-addresses
Original file line number Diff line number Diff line change
@@ -1,17 +1,17 @@
The I2C protocol knows about two kinds of device addresses: normal 7 bit
The I2C protocol knows about two kinds of device addresses: normal 7 bit
addresses, and an extended set of 10 bit addresses. The sets of addresses
do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
address 0x10 (though a single device could respond to both of them). You
select a 10 bit address by adding an extra byte after the address
byte:
S Addr7 Rd/Wr ....
S Addr7 Rd/Wr ....
becomes
S 11110 Addr10 Rd/Wr
S is the start bit, Rd/Wr the read/write bit, and if you count the number
of bits, you will see the there are 8 after the S bit for 7 bit addresses,
and 16 after the S bit for 10 bit addresses.

WARNING! The current 10 bit address support is EXPERIMENTAL. There are
WARNING! The current 10 bit address support is EXPERIMENTAL. There are
several places in the code that will cause SEVERE PROBLEMS with 10 bit
addresses, even though there is some basic handling and hooks. Also,
almost no supported adapter handles the 10 bit addresses correctly.
Expand Down
3 changes: 1 addition & 2 deletions trunk/MAINTAINERS
Original file line number Diff line number Diff line change
Expand Up @@ -3503,9 +3503,8 @@ F: arch/powerpc/platforms/83xx/

LINUX FOR POWERPC PA SEMI PWRFICIENT
M: Olof Johansson <olof@lixom.net>
W: http://www.pasemi.com/
L: linuxppc-dev@ozlabs.org
S: Supported
S: Maintained
F: arch/powerpc/platforms/pasemi/
F: drivers/*/*pasemi*
F: drivers/*/*/*pasemi*
Expand Down
4 changes: 0 additions & 4 deletions trunk/arch/powerpc/include/asm/macio.h
Original file line number Diff line number Diff line change
Expand Up @@ -123,10 +123,6 @@ static inline struct pci_dev *macio_get_pci_dev(struct macio_dev *mdev)
*/
struct macio_driver
{
char *name;
struct of_device_id *match_table;
struct module *owner;

int (*probe)(struct macio_dev* dev, const struct of_device_id *match);
int (*remove)(struct macio_dev* dev);

Expand Down
14 changes: 2 additions & 12 deletions trunk/arch/powerpc/kernel/kprobes.c
Original file line number Diff line number Diff line change
Expand Up @@ -378,17 +378,6 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p,
* single-stepped a copy of the instruction. The address of this
* copy is p->ainsn.insn.
*/
static void __kprobes resume_execution(struct kprobe *p, struct pt_regs *regs)
{
int ret;
unsigned int insn = *p->ainsn.insn;

regs->nip = (unsigned long)p->addr;
ret = emulate_step(regs, insn);
if (ret == 0)
regs->nip = (unsigned long)p->addr + 4;
}

static int __kprobes post_kprobe_handler(struct pt_regs *regs)
{
struct kprobe *cur = kprobe_running();
Expand All @@ -406,7 +395,8 @@ static int __kprobes post_kprobe_handler(struct pt_regs *regs)
cur->post_handler(cur, regs, 0);
}

resume_execution(cur, regs);
/* Adjust nip to after the single-stepped instruction */
regs->nip = (unsigned long)cur->addr + 4;
regs->msr |= kcb->kprobe_saved_msr;

/*Restore back the original saved kprobes variables and continue. */
Expand Down
2 changes: 1 addition & 1 deletion trunk/arch/powerpc/platforms/cell/iommu.c
Original file line number Diff line number Diff line change
Expand Up @@ -1066,7 +1066,7 @@ static int __init cell_iommu_fixed_mapping_init(void)
fbase = _ALIGN_UP(fbase, 1 << IO_SEGMENT_SHIFT);
fsize = lmb_phys_mem_size();

if ((fbase + fsize) <= 0x800000000)
if ((fbase + fsize) <= 0x800000000ul)
hbase = 0; /* use the device tree window */
else {
/* If we're over 32 GB we need to cheat. We can't map all of
Expand Down
2 changes: 1 addition & 1 deletion trunk/arch/powerpc/sysdev/fsl_msi.c
Original file line number Diff line number Diff line change
Expand Up @@ -347,7 +347,7 @@ static int __devinit fsl_of_msi_probe(struct of_device *dev,
goto error_out;
}
offset = 0;
p = of_get_property(dev->node, "msi-available-ranges", &len);
p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
if (p)
offset = *p / IRQS_PER_MSI_REG;

Expand Down
2 changes: 1 addition & 1 deletion trunk/arch/powerpc/sysdev/fsl_rio.c
Original file line number Diff line number Diff line change
Expand Up @@ -1426,7 +1426,7 @@ int fsl_rio_setup(struct of_device *dev)
port->iores.flags = IORESOURCE_MEM;
port->iores.name = "rio_io_win";

priv->pwirq = irq_of_parse_and_map(dev->node, 0);
priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0);
priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2);
priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3);
priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4);
Expand Down
16 changes: 9 additions & 7 deletions trunk/arch/x86/kernel/amd_iommu.c
Original file line number Diff line number Diff line change
Expand Up @@ -1487,6 +1487,7 @@ static int __attach_device(struct device *dev,
struct protection_domain *domain)
{
struct iommu_dev_data *dev_data, *alias_data;
int ret;

dev_data = get_dev_data(dev);
alias_data = get_dev_data(dev_data->alias);
Expand All @@ -1498,13 +1499,14 @@ static int __attach_device(struct device *dev,
spin_lock(&domain->lock);

/* Some sanity checks */
ret = -EBUSY;
if (alias_data->domain != NULL &&
alias_data->domain != domain)
return -EBUSY;
goto out_unlock;

if (dev_data->domain != NULL &&
dev_data->domain != domain)
return -EBUSY;
goto out_unlock;

/* Do real assignment */
if (dev_data->alias != dev) {
Expand All @@ -1520,10 +1522,14 @@ static int __attach_device(struct device *dev,

atomic_inc(&dev_data->bind);

ret = 0;

out_unlock:

/* ready */
spin_unlock(&domain->lock);

return 0;
return ret;
}

/*
Expand Down Expand Up @@ -2324,10 +2330,6 @@ int __init amd_iommu_init_dma_ops(void)

iommu_detected = 1;
swiotlb = 0;
#ifdef CONFIG_GART_IOMMU
gart_iommu_aperture_disabled = 1;
gart_iommu_aperture = 0;
#endif

/* Make the driver finally visible to the drivers */
dma_ops = &amd_iommu_dma_ops;
Expand Down
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