---

yaml
---
r: 268625
b: refs/heads/master
c: 776dddc
h: refs/heads/master
i:
  268623: e1d79cc
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: f32f116bdae1b6f8913b333694d4014aa9b6f7e6
+refs/heads/master: 776dddc52d67e67c74d7cc9a60e915a4dab73a3d

trunk/drivers/staging/brcm80211/brcmsmac/Makefile

@@ -15,7 +15,8 @@
 # OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 # CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-ccflags-y :=				\
+ccflags-y := \
+	-D__CHECK_ENDIAN__ \
 	-Idrivers/staging/brcm80211/brcmsmac \
 	-Idrivers/staging/brcm80211/brcmsmac/phy \
 	-Idrivers/staging/brcm80211/include

trunk/drivers/staging/brcm80211/brcmsmac/d11.h

@@ -745,37 +745,37 @@ struct cck_phy_hdr {
 
 /* TX DMA buffer header */
 struct d11txh {
-	u16 MacTxControlLow;	/* 0x0 */
-	u16 MacTxControlHigh;	/* 0x1 */
-	u16 MacFrameControl;	/* 0x2 */
-	u16 TxFesTimeNormal;	/* 0x3 */
-	u16 PhyTxControlWord;	/* 0x4 */
-	u16 PhyTxControlWord_1;	/* 0x5 */
-	u16 PhyTxControlWord_1_Fbr;	/* 0x6 */
-	u16 PhyTxControlWord_1_Rts;	/* 0x7 */
-	u16 PhyTxControlWord_1_FbrRts;	/* 0x8 */
-	u16 MainRates;	/* 0x9 */
-	u16 XtraFrameTypes;	/* 0xa */
+	__le16 MacTxControlLow;	/* 0x0 */
+	__le16 MacTxControlHigh;	/* 0x1 */
+	__le16 MacFrameControl;	/* 0x2 */
+	__le16 TxFesTimeNormal;	/* 0x3 */
+	__le16 PhyTxControlWord;	/* 0x4 */
+	__le16 PhyTxControlWord_1;	/* 0x5 */
+	__le16 PhyTxControlWord_1_Fbr;	/* 0x6 */
+	__le16 PhyTxControlWord_1_Rts;	/* 0x7 */
+	__le16 PhyTxControlWord_1_FbrRts;	/* 0x8 */
+	__le16 MainRates;	/* 0x9 */
+	__le16 XtraFrameTypes;	/* 0xa */
 	u8 IV[16];		/* 0x0b - 0x12 */
 	u8 TxFrameRA[6];	/* 0x13 - 0x15 */
-	u16 TxFesTimeFallback;	/* 0x16 */
+	__le16 TxFesTimeFallback;	/* 0x16 */
 	u8 RTSPLCPFallback[6];	/* 0x17 - 0x19 */
-	u16 RTSDurFallback;	/* 0x1a */
+	__le16 RTSDurFallback;	/* 0x1a */
 	u8 FragPLCPFallback[6];	/* 0x1b - 1d */
-	u16 FragDurFallback;	/* 0x1e */
-	u16 MModeLen;	/* 0x1f */
-	u16 MModeFbrLen;	/* 0x20 */
-	u16 TstampLow;	/* 0x21 */
-	u16 TstampHigh;	/* 0x22 */
-	u16 ABI_MimoAntSel;	/* 0x23 */
-	u16 PreloadSize;	/* 0x24 */
-	u16 AmpduSeqCtl;	/* 0x25 */
-	u16 TxFrameID;	/* 0x26 */
-	u16 TxStatus;	/* 0x27 */
-	u16 MaxNMpdus;	/* 0x28 */
-	u16 MaxABytes_MRT;	/* 0x29 */
-	u16 MaxABytes_FBR;	/* 0x2a */
-	u16 MinMBytes;	/* 0x2b */
+	__le16 FragDurFallback;	/* 0x1e */
+	__le16 MModeLen;	/* 0x1f */
+	__le16 MModeFbrLen;	/* 0x20 */
+	__le16 TstampLow;	/* 0x21 */
+	__le16 TstampHigh;	/* 0x22 */
+	__le16 ABI_MimoAntSel;	/* 0x23 */
+	__le16 PreloadSize;	/* 0x24 */
+	__le16 AmpduSeqCtl;	/* 0x25 */
+	__le16 TxFrameID;	/* 0x26 */
+	__le16 TxStatus;	/* 0x27 */
+	__le16 MaxNMpdus;	/* 0x28 */
+	__le16 MaxABytes_MRT;	/* 0x29 */
+	__le16 MaxABytes_FBR;	/* 0x2a */
+	__le16 MinMBytes;	/* 0x2b */
 	u8 RTSPhyHeader[D11_PHY_HDR_LEN];	/* 0x2c - 0x2e */
 	struct ieee80211_rts rts_frame;	/* 0x2f - 0x36 */
 	u16 PAD;		/* 0x37 */
@@ -1379,6 +1379,21 @@ struct shm_acparams {
  * RxTSFTime: RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY
  * RxChan: gain code, channel radio code, and phy type
  */
+struct d11rxhdr_le {
+	__le16 RxFrameSize;
+	u16 PAD;
+	__le16 PhyRxStatus_0;
+	__le16 PhyRxStatus_1;
+	__le16 PhyRxStatus_2;
+	__le16 PhyRxStatus_3;
+	__le16 PhyRxStatus_4;
+	__le16 PhyRxStatus_5;
+	__le16 RxStatus1;
+	__le16 RxStatus2;
+	__le16 RxTSFTime;
+	__le16 RxChan;
+} __packed;
+
 struct d11rxhdr {
 	u16 RxFrameSize;
 	u16 PAD;
@@ -1392,20 +1407,18 @@ struct d11rxhdr {
 	u16 RxStatus2;
 	u16 RxTSFTime;
 	u16 RxChan;
-} __packed;
+};
 
 /*
  * rxhdr: received frame header data
- * tsf_l: TSF_L reading
- * rssi: computed instanteneous rssi in BMAC
+ * rssi: rssi computed by PHY
  * rxpwr0: obsoleted, place holder for legacy ROM code. use rxpwr[]
  * rxpwr1: obsoleted, place holder for legacy ROM code. use rxpwr[]
  * do_rssi_ma: do per-pkt sampling for per-antenna ma in HIGH
  * rxpwr: rssi for supported antennas
  */
 struct brcms_d11rxhdr {
-	struct d11rxhdr rxhdr;
-	u32 tsf_l;
+	struct d11rxhdr rxh_cpu;
 	s8 rssi;
 	s8 rxpwr0;
 	s8 rxpwr1;

trunk/drivers/staging/brcm80211/brcmsmac/dma.c

@@ -206,10 +206,10 @@
  * Descriptors are only read by the hardware, never written back.
  */
 struct dma64desc {
-	u32 ctrl1;	/* misc control bits & bufcount */
-	u32 ctrl2;	/* buffer count and address extension */
-	u32 addrlow;	/* memory address of the date buffer, bits 31:0 */
-	u32 addrhigh;	/* memory address of the date buffer, bits 63:32 */
+	__le32 ctrl1;	/* misc control bits & bufcount */
+	__le32 ctrl2;	/* buffer count and address extension */
+	__le32 addrlow;	/* memory address of the date buffer, bits 31:0 */
+	__le32 addrhigh; /* memory address of the date buffer, bits 63:32 */
 };
 
 /* dma engine software state */
@@ -295,15 +295,18 @@ struct dma_info {
 static uint dma_msg_level;
 
 /* Check for odd number of 1's */
-static u32 parity32(u32 data)
+static u32 parity32(__le32 data)
 {
-	data ^= data >> 16;
-	data ^= data >> 8;
-	data ^= data >> 4;
-	data ^= data >> 2;
-	data ^= data >> 1;
+	/* no swap needed for counting 1's */
+	u32 par_data = *(u32 *)&data;
 
-	return data & 1;
+	par_data ^= par_data >> 16;
+	par_data ^= par_data >> 8;
+	par_data ^= par_data >> 4;
+	par_data ^= par_data >> 2;
+	par_data ^= par_data >> 1;
+
+	return par_data & 1;
 }
 
 static bool dma64_dd_parity(struct dma64desc *dd)
@@ -873,13 +876,13 @@ static struct sk_buff *dma64_getnextrxp(struct dma_info *di, bool forceall)
 	rxp = di->rxp[i];
 	di->rxp[i] = NULL;
 
-	pa = cpu_to_le32(di->rxd64[i].addrlow) - di->dataoffsetlow;
+	pa = le32_to_cpu(di->rxd64[i].addrlow) - di->dataoffsetlow;
 
 	/* clear this packet from the descriptor ring */
 	pci_unmap_single(di->pbus, pa, di->rxbufsize, PCI_DMA_FROMDEVICE);
 
-	di->rxd64[i].addrlow = 0xdeadbeef;
-	di->rxd64[i].addrhigh = 0xdeadbeef;
+	di->rxd64[i].addrlow = cpu_to_le32(0xdeadbeef);
+	di->rxd64[i].addrhigh = cpu_to_le32(0xdeadbeef);
 
 	di->rxin = nextrxd(di, i);
 
@@ -917,7 +920,7 @@ struct sk_buff *dma_rx(struct dma_pub *pub)
 	if (head == NULL)
 		return NULL;
 
-	len = le16_to_cpu(*(u16 *) (head->data));
+	len = le16_to_cpu(*(__le16 *) (head->data));
 	DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
 	dma_spin_for_len(len, head);
 
@@ -1367,14 +1370,14 @@ struct sk_buff *dma_getnexttxp(struct dma_pub *pub, enum txd_range range)
 		dma_addr_t pa;
 		uint size;
 
-		pa = cpu_to_le32(di->txd64[i].addrlow) - di->dataoffsetlow;
+		pa = le32_to_cpu(di->txd64[i].addrlow) - di->dataoffsetlow;
 
 		size =
-		    (cpu_to_le32(di->txd64[i].ctrl2) &
+		    (le32_to_cpu(di->txd64[i].ctrl2) &
 		     D64_CTRL2_BC_MASK);
 
-		di->txd64[i].addrlow = 0xdeadbeef;
-		di->txd64[i].addrhigh = 0xdeadbeef;
+		di->txd64[i].addrlow = cpu_to_le32(0xdeadbeef);
+		di->txd64[i].addrhigh = cpu_to_le32(0xdeadbeef);
 
 		txp = di->txp[i];
 		di->txp[i] = NULL;

trunk/drivers/staging/brcm80211/brcmsmac/mac80211_if.c

@@ -89,9 +89,9 @@
 }
 
 struct firmware_hdr {
-	u32 offset;
-	u32 len;
-	u32 idx;
+	__le32 offset;
+	__le32 len;
+	__le32 idx;
 };
 
 static const char * const brcms_firmwares[MAX_FW_IMAGES] = {
@@ -243,7 +243,7 @@ static const struct ieee80211_supported_band brcms_band_2GHz_nphy_template = {
 		   .mcs = {
 			   /* placeholders for now */
 			   .rx_mask = {0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0},
-			   .rx_highest = 500,
+			   .rx_highest = cpu_to_le16(500),
 			   .tx_params = IEEE80211_HT_MCS_TX_DEFINED}
 		   }
 };
@@ -265,7 +265,7 @@ static const struct ieee80211_supported_band brcms_band_5GHz_nphy_template = {
 		   .mcs = {
 			   /* placeholders for now */
 			   .rx_mask = {0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0},
-			   .rx_highest = 500,
+			   .rx_highest = cpu_to_le16(500),
 			   .tx_params = IEEE80211_HT_MCS_TX_DEFINED}
 		   }
 };
@@ -1625,7 +1625,7 @@ int brcms_ucode_init_uint(struct brcms_info *wl, u32 *data, u32 idx)
 						  "ERROR: fw hdr len\n");
 					return -ENOMSG;
 				}
-				*data = le32_to_cpu(*((u32 *) pdata));
+				*data = le32_to_cpu(*((__le32 *) pdata));
 				return 0;
 			}
 		}