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yaml
---
r: 327964
b: refs/heads/master
c: 9aa49ea
h: refs/heads/master
v: v3
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Sujith Manoharan authored and John W. Linville committed Sep 11, 2012
1 parent b2f31ab commit c33baa7
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Showing 4 changed files with 52 additions and 56 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: b7f597668657c9c9579dbdff9692aea3e8e9bf5a
refs/heads/master: 9aa49ea3f5999a6a36823bd259892088896af140
27 changes: 12 additions & 15 deletions trunk/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
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Expand Up @@ -3627,35 +3627,32 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
regval &= (~AR_ANT_DIV_CTRL_ALL);
regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
/* enable_lnadiv */
regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
regval |= ((value >> 6) & 0x1) <<
AR_PHY_9485_ANT_DIV_LNADIV_S;
regval &= (~AR_PHY_ANT_DIV_LNADIV);
regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

/*enable fast_div */
regval = REG_READ(ah, AR_PHY_CCK_DETECT);
regval &= (~AR_FAST_DIV_ENABLE);
regval |= ((value >> 7) & 0x1) <<
AR_FAST_DIV_ENABLE_S;
regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
ant_div_ctl1 =
ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
/* check whether antenna diversity is enabled */
if ((ant_div_ctl1 >> 0x6) == 0x3) {
regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
/*
* clear bits 25-30 main_lnaconf, alt_lnaconf,
* main_tb, alt_tb
*/
regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
AR_PHY_9485_ANT_DIV_ALT_LNACONF |
AR_PHY_9485_ANT_DIV_ALT_GAINTB |
AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
AR_PHY_ANT_DIV_ALT_LNACONF |
AR_PHY_ANT_DIV_ALT_GAINTB |
AR_PHY_ANT_DIV_MAIN_GAINTB));
/* by default use LNA1 for the main antenna */
regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
regval |= (AR_PHY_ANT_DIV_LNA1 <<
AR_PHY_ANT_DIV_MAIN_LNACONF_S);
regval |= (AR_PHY_ANT_DIV_LNA2 <<
AR_PHY_ANT_DIV_ALT_LNACONF_S);
REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
}

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45 changes: 22 additions & 23 deletions trunk/drivers/net/wireless/ath/ath9k/ar9003_phy.c
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Expand Up @@ -1276,17 +1276,17 @@ static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
}

static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
struct ath_hw_antcomb_conf *antconf)
struct ath_hw_antcomb_conf *antconf)
{
u32 regval;

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
AR_PHY_ANT_DIV_MAIN_LNACONF_S;
antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
AR_PHY_ANT_DIV_ALT_LNACONF_S;
antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
AR_PHY_ANT_FAST_DIV_BIAS_S;

if (AR_SREV_9330_11(ah)) {
antconf->lna1_lna2_delta = -9;
Expand All @@ -1306,22 +1306,21 @@ static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
u32 regval;

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
AR_PHY_9485_ANT_DIV_ALT_LNACONF |
AR_PHY_9485_ANT_FAST_DIV_BIAS |
AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
AR_PHY_9485_ANT_DIV_ALT_GAINTB);
regval |= ((antconf->main_lna_conf <<
AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
& AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
& AR_PHY_9485_ANT_DIV_ALT_LNACONF);
regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
& AR_PHY_9485_ANT_FAST_DIV_BIAS);
regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
& AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
& AR_PHY_9485_ANT_DIV_ALT_GAINTB);
regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
AR_PHY_ANT_DIV_ALT_LNACONF |
AR_PHY_ANT_FAST_DIV_BIAS |
AR_PHY_ANT_DIV_MAIN_GAINTB |
AR_PHY_ANT_DIV_ALT_GAINTB);
regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
& AR_PHY_ANT_DIV_MAIN_LNACONF);
regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
& AR_PHY_ANT_DIV_ALT_LNACONF);
regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
& AR_PHY_ANT_FAST_DIV_BIAS);
regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
& AR_PHY_ANT_DIV_MAIN_GAINTB);
regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
& AR_PHY_ANT_DIV_ALT_GAINTB);

REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
}
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34 changes: 17 additions & 17 deletions trunk/drivers/net/wireless/ath/ath9k/ar9003_phy.h
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Expand Up @@ -280,23 +280,23 @@
#define AR_ANT_DIV_ENABLE_S 24


#define AR_PHY_9485_ANT_FAST_DIV_BIAS 0x00007e00
#define AR_PHY_9485_ANT_FAST_DIV_BIAS_S 9
#define AR_PHY_9485_ANT_DIV_LNADIV 0x01000000
#define AR_PHY_9485_ANT_DIV_LNADIV_S 24
#define AR_PHY_9485_ANT_DIV_ALT_LNACONF 0x06000000
#define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S 25
#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF 0x18000000
#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S 27
#define AR_PHY_9485_ANT_DIV_ALT_GAINTB 0x20000000
#define AR_PHY_9485_ANT_DIV_ALT_GAINTB_S 29
#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB 0x40000000
#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S 30

#define AR_PHY_9485_ANT_DIV_LNA1_MINUS_LNA2 0x0
#define AR_PHY_9485_ANT_DIV_LNA2 0x1
#define AR_PHY_9485_ANT_DIV_LNA1 0x2
#define AR_PHY_9485_ANT_DIV_LNA1_PLUS_LNA2 0x3
#define AR_PHY_ANT_FAST_DIV_BIAS 0x00007e00
#define AR_PHY_ANT_FAST_DIV_BIAS_S 9
#define AR_PHY_ANT_DIV_LNADIV 0x01000000
#define AR_PHY_ANT_DIV_LNADIV_S 24
#define AR_PHY_ANT_DIV_ALT_LNACONF 0x06000000
#define AR_PHY_ANT_DIV_ALT_LNACONF_S 25
#define AR_PHY_ANT_DIV_MAIN_LNACONF 0x18000000
#define AR_PHY_ANT_DIV_MAIN_LNACONF_S 27
#define AR_PHY_ANT_DIV_ALT_GAINTB 0x20000000
#define AR_PHY_ANT_DIV_ALT_GAINTB_S 29
#define AR_PHY_ANT_DIV_MAIN_GAINTB 0x40000000
#define AR_PHY_ANT_DIV_MAIN_GAINTB_S 30

#define AR_PHY_ANT_DIV_LNA1_MINUS_LNA2 0x0
#define AR_PHY_ANT_DIV_LNA2 0x1
#define AR_PHY_ANT_DIV_LNA1 0x2
#define AR_PHY_ANT_DIV_LNA1_PLUS_LNA2 0x3

#define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c)
#define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30)
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