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r: 227147
b: refs/heads/master
c: 45bbaae
h: refs/heads/master
i:
  227145: 0a9c6ff
  227143: 4d1a744
v: v3
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Paul Mundt committed Nov 18, 2010
1 parent cefea93 commit c37511e
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2 changes: 1 addition & 1 deletion [refs]
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---
refs/heads/master: 6d9598e24d50a8c72f48a3864327484a30aaee44
refs/heads/master: 45bbaae0dcddc275594e23f108cb68869eae7433
89 changes: 89 additions & 0 deletions trunk/arch/arm/mach-shmobile/include/mach/entry-macro-gic.S
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/*
* Copyright (C) 2010 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <mach/hardware.h>
#include <asm/hardware/gic.h>

.macro disable_fiq
.endm

.macro get_irqnr_preamble, base, tmp
ldr \base, =(0xf0000100)
.endm

.macro arch_ret_to_user, tmp1, tmp2
.endm

/*
* The interrupt numbering scheme is defined in the
* interrupt controller spec. To wit:
*
* Interrupts 0-15 are IPI
* 16-28 are reserved
* 29-31 are local. We allow 30 to be used for the watchdog.
* 32-1020 are global
* 1021-1022 are reserved
* 1023 is "spurious" (no interrupt)
*
* For now, we ignore all local interrupts so only return an
* interrupt if it's between 30 and 1020. The test_for_ipi
* routine below will pick up on IPIs.
*
* A simple read from the controller will tell us the number of
* the highest priority enabled interrupt. We then just need to
* check whether it is in the valid range for an IRQ (30-1020
* inclusive).
*/

.macro get_irqnr_and_base, irqnr, irqstat, base, tmp

ldr \irqstat, [\base, #GIC_CPU_INTACK]
/* bits 12-10 = src CPU, 9-0 = int # */

ldr \tmp, =1021
bic \irqnr, \irqstat, #0x1c00
cmp \irqnr, #29
cmpcc \irqnr, \irqnr
cmpne \irqnr, \tmp
cmpcs \irqnr, \irqnr

.endm

/*
* We assume that irqstat (the raw value of the IRQ acknowledge
* register) is preserved from the macro above.
* If there is an IPI, we immediately signal end of interrupt on the
* controller, since this requires the original irqstat value which
* we won't easily be able to recreate later.
*/

.macro test_for_ipi, irqnr, irqstat, base, tmp
bic \irqnr, \irqstat, #0x1c00
cmp \irqnr, #16
strcc \irqstat, [\base, #GIC_CPU_EOI]
cmpcs \irqnr, \irqnr
.endm

/* As above, this assumes that irqstat and base are preserved.. */

.macro test_for_ltirq, irqnr, irqstat, base, tmp
bic \irqnr, \irqstat, #0x1c00
mov \tmp, #0
cmp \irqnr, #29
moveq \tmp, #1
streq \irqstat, [\base, #GIC_CPU_EOI]
cmp \tmp, #0
.endm
39 changes: 39 additions & 0 deletions trunk/arch/arm/mach-shmobile/include/mach/entry-macro-intc.S
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/*
* Copyright (C) 2008 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <mach/hardware.h>
#include <mach/irqs.h>

.macro disable_fiq
.endm

.macro get_irqnr_preamble, base, tmp
ldr \base, =INTFLGA
.endm

.macro arch_ret_to_user, tmp1, tmp2
.endm

.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqnr, [\base]
cmp \irqnr, #0
beq 1000f
/* intevt to irq number */
lsr \irqnr, \irqnr, #0x5
subs \irqnr, \irqnr, #16

1000:
.endm
104 changes: 4 additions & 100 deletions trunk/arch/arm/mach-shmobile/include/mach/entry-macro.S
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/*
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (C) 2010 Paul Mundt
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Expand All @@ -14,104 +14,8 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <mach/hardware.h>
#include <mach/irqs.h>

.macro disable_fiq
.endm

#if !defined(CONFIG_ARCH_SH73A0)
.macro get_irqnr_preamble, base, tmp
ldr \base, =INTFLGA
.endm

.macro arch_ret_to_user, tmp1, tmp2
.endm

.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqnr, [\base]
cmp \irqnr, #0
beq 1000f
/* intevt to irq number */
lsr \irqnr, \irqnr, #0x5
subs \irqnr, \irqnr, #16

1000:
.endm
#if defined(CONFIG_ARM_GIC)
#include <mach/entry-macro-gic.S>
#else
/*
* arch/arm/mach-realview/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for RealView platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware/gic.h>

.macro get_irqnr_preamble, base, tmp
ldr \base, =(0xf0000100)
.endm

.macro arch_ret_to_user, tmp1, tmp2
.endm

/*
* The interrupt numbering scheme is defined in the
* interrupt controller spec. To wit:
*
* Interrupts 0-15 are IPI
* 16-28 are reserved
* 29-31 are local. We allow 30 to be used for the watchdog.
* 32-1020 are global
* 1021-1022 are reserved
* 1023 is "spurious" (no interrupt)
*
* For now, we ignore all local interrupts so only return an interrupt if it's
* between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
*
* A simple read from the controller will tell us the number of the highest
* priority enabled interrupt. We then just need to check whether it is in the
* valid range for an IRQ (30-1020 inclusive).
*/

.macro get_irqnr_and_base, irqnr, irqstat, base, tmp

ldr \irqstat, [\base, #GIC_CPU_INTACK]
/* bits 12-10 = src CPU, 9-0 = int # */

ldr \tmp, =1021
bic \irqnr, \irqstat, #0x1c00
cmp \irqnr, #29
cmpcc \irqnr, \irqnr
cmpne \irqnr, \tmp
cmpcs \irqnr, \irqnr

.endm

/* We assume that irqstat (the raw value of the IRQ acknowledge
* register) is preserved from the macro above.
* If there is an IPI, we immediately signal end of interrupt on the
* controller, since this requires the original irqstat value which
* we won't easily be able to recreate later.
*/

.macro test_for_ipi, irqnr, irqstat, base, tmp
bic \irqnr, \irqstat, #0x1c00
cmp \irqnr, #16
strcc \irqstat, [\base, #GIC_CPU_EOI]
cmpcs \irqnr, \irqnr
.endm

/* As above, this assumes that irqstat and base are preserved.. */

.macro test_for_ltirq, irqnr, irqstat, base, tmp
bic \irqnr, \irqstat, #0x1c00
mov \tmp, #0
cmp \irqnr, #29
moveq \tmp, #1
streq \irqstat, [\base, #GIC_CPU_EOI]
cmp \tmp, #0
.endm
#include <mach/entry-macro-intc.S>
#endif

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