Skip to content

Commit

Permalink
Merge branch 'upstream'
Browse files Browse the repository at this point in the history
  • Loading branch information
Jeff Garzik committed Oct 9, 2005
2 parents cedc9a4 + 3d3467f commit c4052da
Show file tree
Hide file tree
Showing 135 changed files with 4,484 additions and 1,630 deletions.
1,072 changes: 1,072 additions & 0 deletions Documentation/DocBook/libata.tmpl

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion arch/arm/kernel/sys_arm.c
Original file line number Diff line number Diff line change
Expand Up @@ -305,7 +305,7 @@ long execve(const char *filename, char **argv, char **envp)
"Ir" (THREAD_START_SP - sizeof(regs)),
"r" (&regs),
"Ir" (sizeof(regs))
: "r0", "r1", "r2", "r3", "ip", "memory");
: "r0", "r1", "r2", "r3", "ip", "lr", "memory");

out:
return ret;
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/kernel/traps.c
Original file line number Diff line number Diff line change
Expand Up @@ -504,7 +504,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)

bad_access:
spin_unlock(&mm->page_table_lock);
/* simulate a read access fault */
/* simulate a write access fault */
do_DataAbort(addr, 15 + (1 << 11), regs);
return -1;
}
Expand Down
23 changes: 12 additions & 11 deletions arch/arm/mach-imx/generic.c
Original file line number Diff line number Diff line change
Expand Up @@ -28,14 +28,15 @@
#include <linux/module.h>
#include <asm/arch/imxfb.h>
#include <asm/hardware.h>
#include <asm/arch/imx-regs.h>

#include <asm/mach/map.h>

void imx_gpio_mode(int gpio_mode)
{
unsigned int pin = gpio_mode & GPIO_PIN_MASK;
unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5;
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10;
unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
unsigned int tmp;

/* Pullup enable */
Expand All @@ -57,7 +58,7 @@ void imx_gpio_mode(int gpio_mode)
GPR(port) &= ~(1<<pin);

/* use as gpio? */
if( ocr == 3 )
if(gpio_mode & GPIO_GIUS)
GIUS(port) |= (1<<pin);
else
GIUS(port) &= ~(1<<pin);
Expand All @@ -72,20 +73,20 @@ void imx_gpio_mode(int gpio_mode)
tmp |= (ocr << (pin*2));
OCR1(port) = tmp;

if( gpio_mode & GPIO_AOUT )
ICONFA1(port) &= ~( 3<<(pin*2));
if( gpio_mode & GPIO_BOUT )
ICONFB1(port) &= ~( 3<<(pin*2));
ICONFA1(port) &= ~( 3<<(pin*2));
ICONFA1(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
ICONFB1(port) &= ~( 3<<(pin*2));
ICONFB1(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
} else {
tmp = OCR2(port);
tmp &= ~( 3<<((pin-16)*2));
tmp |= (ocr << ((pin-16)*2));
OCR2(port) = tmp;

if( gpio_mode & GPIO_AOUT )
ICONFA2(port) &= ~( 3<<((pin-16)*2));
if( gpio_mode & GPIO_BOUT )
ICONFB2(port) &= ~( 3<<((pin-16)*2));
ICONFA2(port) &= ~( 3<<((pin-16)*2));
ICONFA2(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << ((pin-16) * 2);
ICONFB2(port) &= ~( 3<<((pin-16)*2));
ICONFB2(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << ((pin-16) * 2);
}
}

Expand Down
2 changes: 1 addition & 1 deletion arch/arm/mach-imx/mx1ads.c
Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,7 @@ static void __init
mx1ads_init(void)
{
#ifdef CONFIG_LEDS
imx_gpio_mode(GPIO_PORTA | GPIO_OUT | GPIO_GPIO | 2);
imx_gpio_mode(GPIO_PORTA | GPIO_OUT | 2);
#endif
platform_add_devices(devices, ARRAY_SIZE(devices));
}
Expand Down
8 changes: 4 additions & 4 deletions arch/arm/mm/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -370,21 +370,21 @@ config CPU_BIG_ENDIAN

config CPU_ICACHE_DISABLE
bool "Disable I-Cache"
depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020
depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
help
Say Y here to disable the processor instruction cache. Unless
you have a reason not to or are unsure, say N.

config CPU_DCACHE_DISABLE
bool "Disable D-Cache"
depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020
depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
help
Say Y here to disable the processor data cache. Unless
you have a reason not to or are unsure, say N.

config CPU_DCACHE_WRITETHROUGH
bool "Force write through D-cache"
depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DCACHE_DISABLE
depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
default y if CPU_ARM925T
help
Say Y here to use the data cache in writethrough mode. Unless you
Expand All @@ -399,7 +399,7 @@ config CPU_CACHE_ROUND_ROBIN

config CPU_BPREDICT_DISABLE
bool "Disable branch prediction"
depends on CPU_ARM1020
depends on CPU_ARM1020 || CPU_V6
help
Say Y here to disable branch prediction. If unsure, say N.

Expand Down
5 changes: 5 additions & 0 deletions arch/ia64/kernel/mca.c
Original file line number Diff line number Diff line change
Expand Up @@ -1016,6 +1016,11 @@ ia64_mca_cmc_int_handler(int cmc_irq, void *arg, struct pt_regs *ptregs)

cmc_polling_enabled = 1;
spin_unlock(&cmc_history_lock);
/* If we're being hit with CMC interrupts, we won't
* ever execute the schedule_work() below. Need to
* disable CMC interrupts on this processor now.
*/
ia64_mca_cmc_vector_disable(NULL);
schedule_work(&cmc_disable_work);

/*
Expand Down
2 changes: 1 addition & 1 deletion arch/ppc/platforms/pmac_time.c
Original file line number Diff line number Diff line change
Expand Up @@ -195,7 +195,7 @@ via_calibrate_decr(void)
;
dend = get_dec();

tb_ticks_per_jiffy = (dstart - dend) / (6 * (HZ/100));
tb_ticks_per_jiffy = (dstart - dend) / ((6 * HZ)/100);
tb_to_us = mulhwu_scale_factor(dstart - dend, 60000);

printk(KERN_INFO "via_calibrate_decr: ticks per jiffy = %u (%u ticks)\n",
Expand Down
56 changes: 0 additions & 56 deletions arch/sparc/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -25,62 +25,6 @@ source "init/Kconfig"

menu "General machine setup"

config VT
bool
select INPUT
default y
---help---
If you say Y here, you will get support for terminal devices with
display and keyboard devices. These are called "virtual" because you
can run several virtual terminals (also called virtual consoles) on
one physical terminal. This is rather useful, for example one
virtual terminal can collect system messages and warnings, another
one can be used for a text-mode user session, and a third could run
an X session, all in parallel. Switching between virtual terminals
is done with certain key combinations, usually Alt-<function key>.

The setterm command ("man setterm") can be used to change the
properties (such as colors or beeping) of a virtual terminal. The
man page console_codes(4) ("man console_codes") contains the special
character sequences that can be used to change those properties
directly. The fonts used on virtual terminals can be changed with
the setfont ("man setfont") command and the key bindings are defined
with the loadkeys ("man loadkeys") command.

You need at least one virtual terminal device in order to make use
of your keyboard and monitor. Therefore, only people configuring an
embedded system would want to say N here in order to save some
memory; the only way to log into such a system is then via a serial
or network connection.

If unsure, say Y, or else you won't be able to do much with your new
shiny Linux system :-)

config VT_CONSOLE
bool
default y
---help---
The system console is the device which receives all kernel messages
and warnings and which allows logins in single user mode. If you
answer Y here, a virtual terminal (the device used to interact with
a physical terminal) can be used as system console. This is the most
common mode of operations, so you should say Y here unless you want
the kernel messages be output only to a serial port (in which case
you should say Y to "Console on serial port", below).

If you do say Y here, by default the currently visible virtual
terminal (/dev/tty0) will be used as system console. You can change
that with a kernel command line option such as "console=tty3" which
would use the third virtual terminal as system console. (Try "man
bootparam" or see the documentation of your boot loader (lilo or
loadlin) about how to pass options to the kernel at boot time.)

If unsure, say Y.

config HW_CONSOLE
bool
default y

config SMP
bool "Symmetric multi-processing support (does not work on sun4/sun4c)"
depends on BROKEN
Expand Down
2 changes: 1 addition & 1 deletion arch/sparc/kernel/time.c
Original file line number Diff line number Diff line change
Expand Up @@ -457,7 +457,7 @@ void __init time_init(void)
sbus_time_init();
}

extern __inline__ unsigned long do_gettimeoffset(void)
static inline unsigned long do_gettimeoffset(void)
{
return (*master_l10_counter >> 10) & 0x1fffff;
}
Expand Down
2 changes: 1 addition & 1 deletion arch/sparc/mm/srmmu.c
Original file line number Diff line number Diff line change
Expand Up @@ -260,7 +260,7 @@ static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
{ return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }

/* to find an entry in a top-level page table... */
extern inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
static inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
{ return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }

/* Find an entry in the second-level page table.. */
Expand Down
43 changes: 8 additions & 35 deletions arch/sparc64/kernel/entry.S
Original file line number Diff line number Diff line change
Expand Up @@ -97,8 +97,8 @@ do_fpdis:
faddd %f0, %f2, %f4
fmuld %f0, %f2, %f6
ldxa [%g3] ASI_DMMU, %g5
cplus_fptrap_insn_1:
sethi %hi(0), %g2
sethi %hi(sparc64_kern_sec_context), %g2
ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
stxa %g2, [%g3] ASI_DMMU
membar #Sync
add %g6, TI_FPREGS + 0xc0, %g2
Expand Down Expand Up @@ -126,8 +126,8 @@ cplus_fptrap_insn_1:
fzero %f34
ldxa [%g3] ASI_DMMU, %g5
add %g6, TI_FPREGS, %g1
cplus_fptrap_insn_2:
sethi %hi(0), %g2
sethi %hi(sparc64_kern_sec_context), %g2
ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
stxa %g2, [%g3] ASI_DMMU
membar #Sync
add %g6, TI_FPREGS + 0x40, %g2
Expand All @@ -153,8 +153,8 @@ cplus_fptrap_insn_2:
3: mov SECONDARY_CONTEXT, %g3
add %g6, TI_FPREGS, %g1
ldxa [%g3] ASI_DMMU, %g5
cplus_fptrap_insn_3:
sethi %hi(0), %g2
sethi %hi(sparc64_kern_sec_context), %g2
ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
stxa %g2, [%g3] ASI_DMMU
membar #Sync
mov 0x40, %g2
Expand Down Expand Up @@ -319,8 +319,8 @@ do_fptrap_after_fsr:
stx %g3, [%g6 + TI_GSR]
mov SECONDARY_CONTEXT, %g3
ldxa [%g3] ASI_DMMU, %g5
cplus_fptrap_insn_4:
sethi %hi(0), %g2
sethi %hi(sparc64_kern_sec_context), %g2
ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
stxa %g2, [%g3] ASI_DMMU
membar #Sync
add %g6, TI_FPREGS, %g2
Expand All @@ -341,33 +341,6 @@ cplus_fptrap_insn_4:
ba,pt %xcc, etrap
wr %g0, 0, %fprs

cplus_fptrap_1:
sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2

.globl cheetah_plus_patch_fpdis
cheetah_plus_patch_fpdis:
/* We configure the dTLB512_0 for 4MB pages and the
* dTLB512_1 for 8K pages when in context zero.
*/
sethi %hi(cplus_fptrap_1), %o0
lduw [%o0 + %lo(cplus_fptrap_1)], %o1

set cplus_fptrap_insn_1, %o2
stw %o1, [%o2]
flush %o2
set cplus_fptrap_insn_2, %o2
stw %o1, [%o2]
flush %o2
set cplus_fptrap_insn_3, %o2
stw %o1, [%o2]
flush %o2
set cplus_fptrap_insn_4, %o2
stw %o1, [%o2]
flush %o2

retl
nop

/* The registers for cross calls will be:
*
* DATA 0: [low 32-bits] Address of function to call, jmp to this
Expand Down
51 changes: 4 additions & 47 deletions arch/sparc64/kernel/etrap.S
Original file line number Diff line number Diff line change
Expand Up @@ -68,12 +68,8 @@ etrap_irq:

wrpr %g3, 0, %otherwin
wrpr %g2, 0, %wstate
cplus_etrap_insn_1:
sethi %hi(0), %g3
sllx %g3, 32, %g3
cplus_etrap_insn_2:
sethi %hi(0), %g2
or %g3, %g2, %g3
sethi %hi(sparc64_kern_pri_context), %g2
ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
stxa %g3, [%l4] ASI_DMMU
flush %l6
wr %g0, ASI_AIUS, %asi
Expand Down Expand Up @@ -215,12 +211,8 @@ scetrap: rdpr %pil, %g2
mov PRIMARY_CONTEXT, %l4
wrpr %g3, 0, %otherwin
wrpr %g2, 0, %wstate
cplus_etrap_insn_3:
sethi %hi(0), %g3
sllx %g3, 32, %g3
cplus_etrap_insn_4:
sethi %hi(0), %g2
or %g3, %g2, %g3
sethi %hi(sparc64_kern_pri_context), %g2
ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
stxa %g3, [%l4] ASI_DMMU
flush %l6

Expand Down Expand Up @@ -264,38 +256,3 @@ cplus_etrap_insn_4:

#undef TASK_REGOFF
#undef ETRAP_PSTATE1

cplus_einsn_1:
sethi %uhi(CTX_CHEETAH_PLUS_NUC), %g3
cplus_einsn_2:
sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2

.globl cheetah_plus_patch_etrap
cheetah_plus_patch_etrap:
/* We configure the dTLB512_0 for 4MB pages and the
* dTLB512_1 for 8K pages when in context zero.
*/
sethi %hi(cplus_einsn_1), %o0
sethi %hi(cplus_etrap_insn_1), %o2
lduw [%o0 + %lo(cplus_einsn_1)], %o1
or %o2, %lo(cplus_etrap_insn_1), %o2
stw %o1, [%o2]
flush %o2
sethi %hi(cplus_etrap_insn_3), %o2
or %o2, %lo(cplus_etrap_insn_3), %o2
stw %o1, [%o2]
flush %o2

sethi %hi(cplus_einsn_2), %o0
sethi %hi(cplus_etrap_insn_2), %o2
lduw [%o0 + %lo(cplus_einsn_2)], %o1
or %o2, %lo(cplus_etrap_insn_2), %o2
stw %o1, [%o2]
flush %o2
sethi %hi(cplus_etrap_insn_4), %o2
or %o2, %lo(cplus_etrap_insn_4), %o2
stw %o1, [%o2]
flush %o2

retl
nop
Loading

0 comments on commit c4052da

Please sign in to comment.