Skip to content

Commit

Permalink
OMAP2/3: PRM/CM: prefix OMAP2 PRM/CM functions with "omap2_"
Browse files Browse the repository at this point in the history 
Now that OMAP4-specific PRCM functions have been added, distinguish the
existing OMAP2/3-specific PRCM functions by prefixing them with "omap2_".

This patch should not result in any functional change.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Cc: Liam Girdwood <lrg@slimlogic.co.uk>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Rajendra Nayak <rnayak@ti.com>
  • Loading branch information
Paul Walmsley committed Dec 22, 2010
1 parent dac9a77 commit c4d7e58
Show file tree
Hide file tree
Showing 19 changed files with 507 additions and 478 deletions.
10 changes: 5 additions & 5 deletions arch/arm/mach-omap2/clkt2xxx_apll.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,14 +49,14 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)

apll_mask = EN_APLL_LOCKED << clk->enable_bit;

cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);

if ((cval & apll_mask) == apll_mask)
return 0; /* apll already enabled */

cval &= ~apll_mask;
cval |= apll_mask;
cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);

omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
OMAP24XX_CM_IDLEST_VAL, clk->name);
Expand All @@ -83,9 +83,9 @@ static void omap2_clk_apll_disable(struct clk *clk)
{
u32 cval;

cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
}

/* Public data */
Expand All @@ -106,7 +106,7 @@ u32 omap2xxx_get_apll_clkin(void)
{
u32 aplls, srate = 0;

aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
aplls &= OMAP24XX_APLLS_CLKIN_MASK;
aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;

Expand Down
8 changes: 4 additions & 4 deletions arch/arm/mach-omap2/clkt2xxx_dpllcore.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)

core_clk = omap2_get_dpll_rate(clk);

v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
v &= OMAP24XX_CORE_CLK_SRC_MASK;

if (v == CORE_CLK_SRC_32K)
Expand All @@ -73,7 +73,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
{
u32 high, low, core_clk_src;

core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;

if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
Expand Down Expand Up @@ -111,7 +111,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
const struct dpll_data *dd;

cur_rate = omap2xxx_clk_get_core_rate(dclk);
mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
mult &= OMAP24XX_CORE_CLK_SRC_MASK;

if ((rate == (cur_rate / 2)) && (mult == 2)) {
Expand All @@ -136,7 +136,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
dd->div1_mask);
div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
if (rate > low) {
tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
Expand Down
12 changes: 6 additions & 6 deletions arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -133,21 +133,21 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
done_rate = CORE_CLK_SRC_DPLL;

/* MPU divider */
cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);

/* dsp + iva1 div(2420), iva2.1(2430) */
cm_write_mod_reg(prcm->cm_clksel_dsp,
omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,
OMAP24XX_DSP_MOD, CM_CLKSEL);

cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);

/* Major subsystem dividers */
tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
CM_CLKSEL1);

if (cpu_is_omap2430())
cm_write_mod_reg(prcm->cm_clksel_mdm,
omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,
OMAP2430_MDM_MOD, CM_CLKSEL);

/* x2 to enter omap2xxx_sdrc_init_params() */
Expand Down
22 changes: 10 additions & 12 deletions arch/arm/mach-omap2/clockdomain.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,6 @@
*/
#undef DEBUG

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
Expand All @@ -30,7 +29,6 @@
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
#include "cm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"

#include <plat/clock.h>
#include <plat/powerdomain.h>
Expand Down Expand Up @@ -410,7 +408,7 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
pr_debug("clockdomain: hardware will wake up %s when %s wakes "
"up\n", clkdm1->name, clkdm2->name);

prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
}

Expand Down Expand Up @@ -445,7 +443,7 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
pr_debug("clockdomain: hardware will no longer wake up %s "
"after %s wakes up\n", clkdm1->name, clkdm2->name);

prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
}

Expand Down Expand Up @@ -481,7 +479,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
}

/* XXX It's faster to return the atomic wkdep_usecount */
return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP,
return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP,
(1 << clkdm2->dep_bit));
}

Expand Down Expand Up @@ -515,7 +513,7 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
atomic_set(&cd->wkdep_usecount, 0);
}

prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP);
omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP);

return 0;
}
Expand Down Expand Up @@ -554,7 +552,7 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
pr_debug("clockdomain: will prevent %s from sleeping if %s "
"is active\n", clkdm1->name, clkdm2->name);

cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP);
}
Expand Down Expand Up @@ -597,7 +595,7 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
"sleeping if %s is active\n", clkdm1->name,
clkdm2->name);

cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
clkdm1->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP);
}
Expand Down Expand Up @@ -640,7 +638,7 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
}

/* XXX It's faster to return the atomic sleepdep_usecount */
return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP,
(1 << clkdm2->dep_bit));
}
Expand Down Expand Up @@ -678,7 +676,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
atomic_set(&cd->sleepdep_usecount, 0);
}

prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP);

return 0;
Expand Down Expand Up @@ -730,7 +728,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)

if (cpu_is_omap24xx()) {

cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);

} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
Expand Down Expand Up @@ -774,7 +772,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)

if (cpu_is_omap24xx()) {

cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);

} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
Expand Down
Loading

0 comments on commit c4d7e58

Please sign in to comment.