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e1000e: convert enums of register offsets and move #defines to regs.h
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There are enough register offsets to warrant being in their own header
file, and doing so logically separates them from other header file content.
They have been converted from an enumerated data type to #defines as is
done in all the other Intel wired ethernet drivers.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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Bruce Allan authored and Jeff Kirsher committed Feb 5, 2013
1 parent 948f97a commit c556d60
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212 changes: 1 addition & 211 deletions drivers/net/ethernet/intel/e1000e/hw.h
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Expand Up @@ -29,221 +29,11 @@
#ifndef _E1000_HW_H_
#define _E1000_HW_H_

#include "regs.h"
#include "defines.h"

struct e1000_hw;

enum e1e_registers {
E1000_CTRL = 0x00000, /* Device Control - RW */
E1000_STATUS = 0x00008, /* Device Status - RO */
E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
E1000_EERD = 0x00014, /* EEPROM Read - RW */
E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
E1000_FLA = 0x0001C, /* Flash Access - RW */
E1000_MDIC = 0x00020, /* MDI Control - RW */
E1000_SCTL = 0x00024, /* SerDes Control - RW */
E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
E1000_FEXTNVM4 = 0x00024, /* Future Extended NVM 4 - RW */
E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
E1000_FCT = 0x00030, /* Flow Control Type - RW */
E1000_VET = 0x00038, /* VLAN Ether Type - RW */
E1000_FEXTNVM3 = 0x0003C, /* Future Extended NVM 3 - RW */
E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */
E1000_FEXTNVM7 = 0x000E4, /* Future Extended NVM 7 - RW */
E1000_LPIC = 0x000FC, /* Low Power Idle Control - RW */
E1000_RCTL = 0x00100, /* Rx Control - RW */
E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */
E1000_TCTL = 0x00400, /* Tx Control - RW */
E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */
E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
E1000_LEDCTL = 0x00E00, /* LED Control - RW */
E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
#define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
E1000_PBS = 0x01008, /* Packet Buffer Size */
E1000_PBECCSTS = 0x0100C, /* Packet Buffer ECC Status - RW */
E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
E1000_PBA_ECC = 0x01100, /* PBA ECC Register */
E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
/* Convenience macros
*
* Note: "_n" is the queue number of the register to be written to.
*
* Example usage:
* E1000_RDBAL(current_rx_queue)
*/
E1000_RDBAL_BASE = 0x02800, /* Rx Descriptor Base Address Low - RW */
#define E1000_RDBAL(_n) (E1000_RDBAL_BASE + (_n << 8))
E1000_RDBAH_BASE = 0x02804, /* Rx Descriptor Base Address High - RW */
#define E1000_RDBAH(_n) (E1000_RDBAH_BASE + (_n << 8))
E1000_RDLEN_BASE = 0x02808, /* Rx Descriptor Length - RW */
#define E1000_RDLEN(_n) (E1000_RDLEN_BASE + (_n << 8))
E1000_RDH_BASE = 0x02810, /* Rx Descriptor Head - RW */
#define E1000_RDH(_n) (E1000_RDH_BASE + (_n << 8))
E1000_RDT_BASE = 0x02818, /* Rx Descriptor Tail - RW */
#define E1000_RDT(_n) (E1000_RDT_BASE + (_n << 8))
E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
E1000_RADV = 0x0282C, /* Rx Interrupt Absolute Delay Timer - RW */

E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
E1000_TDBAL_BASE = 0x03800, /* Tx Descriptor Base Address Low - RW */
#define E1000_TDBAL(_n) (E1000_TDBAL_BASE + (_n << 8))
E1000_TDBAH_BASE = 0x03804, /* Tx Descriptor Base Address High - RW */
#define E1000_TDBAH(_n) (E1000_TDBAH_BASE + (_n << 8))
E1000_TDLEN_BASE = 0x03808, /* Tx Descriptor Length - RW */
#define E1000_TDLEN(_n) (E1000_TDLEN_BASE + (_n << 8))
E1000_TDH_BASE = 0x03810, /* Tx Descriptor Head - RW */
#define E1000_TDH(_n) (E1000_TDH_BASE + (_n << 8))
E1000_TDT_BASE = 0x03818, /* Tx Descriptor Tail - RW */
#define E1000_TDT(_n) (E1000_TDT_BASE + (_n << 8))
E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
E1000_COLC = 0x04028, /* Collision Count - R/clr */
E1000_DC = 0x04030, /* Defer Count - R/clr */
E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */
E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */
E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */
E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */
E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */
E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */
E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */
E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */
E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */
E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */
E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */
E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */
E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */
E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */
E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */
E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */
E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */
E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */
E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */
E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */
E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */
E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */
E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */
E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */
E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */
E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */
E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */
E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
E1000_IAC = 0x04100, /* Interrupt Assertion Count */
E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
E1000_PCS_LCTL = 0x04208, /* PCS Link Control - RW */
E1000_PCS_LSTAT = 0x0420C, /* PCS Link Status - RO */
E1000_PCS_ANADV = 0x04218, /* AN advertisement - RW */
E1000_PCS_LPAB = 0x0421C, /* Link Partner Ability - RW */
E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
E1000_RFCTL = 0x05008, /* Receive Filter Control */
E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
#define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
#define E1000_RA (E1000_RAL(0))
E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
#define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
E1000_SHRAL_BASE = 0x05438, /* Shared Receive Address Low - RW */
#define E1000_SHRAL(_n) (E1000_SHRAL_BASE + ((_n) * 8))
E1000_SHRAH_BASE = 0x0543C, /* Shared Receive Address High - RW */
#define E1000_SHRAH(_n) (E1000_SHRAH_BASE + ((_n) * 8))
E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
E1000_WUC = 0x05800, /* Wakeup Control - RW */
E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
E1000_WUS = 0x05810, /* Wakeup Status - RO */
E1000_MRQC = 0x05818, /* Multiple Receive Control - RW */
E1000_MANC = 0x05820, /* Management Control - RW */
E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
E1000_CRC_OFFSET = 0x05F50, /* CRC Offset register */
E1000_HOST_IF = 0x08800, /* Host Interface */

E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */
#define E1000_MDEF(_n) (E1000_MDEF_BASE + ((_n) * 4))
E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
E1000_GCR = 0x05B00, /* PCI-Ex Control */
E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */
E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
E1000_SWSM = 0x05B50, /* SW Semaphore */
E1000_FWSM = 0x05B54, /* FW Semaphore */
E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */
E1000_RETA_BASE = 0x05C00, /* Redirection Table - RW */
#define E1000_RETA(_n) (E1000_RETA_BASE + ((_n) * 4))
E1000_RSSRK_BASE = 0x05C80, /* RSS Random Key - RW */
#define E1000_RSSRK(_n) (E1000_RSSRK_BASE + ((_n) * 4))
E1000_FFLT_DBG = 0x05F04, /* Debug Register */
E1000_HICR = 0x08F00, /* Host Interface Control */
E1000_SYSTIML = 0x0B600, /* System time register Low - RO */
E1000_SYSTIMH = 0x0B604, /* System time register High - RO */
E1000_TIMINCA = 0x0B608, /* Increment attributes register - RW */
E1000_TSYNCTXCTL = 0x0B614, /* Tx Time Sync Control register - RW */
E1000_TXSTMPL = 0x0B618, /* Tx timestamp value Low - RO */
E1000_TXSTMPH = 0x0B61C, /* Tx timestamp value High - RO */
E1000_TSYNCRXCTL = 0x0B620, /* Rx Time Sync Control register - RW */
E1000_RXSTMPL = 0x0B624, /* Rx timestamp Low - RO */
E1000_RXSTMPH = 0x0B628, /* Rx timestamp High - RO */
E1000_RXMTRL = 0x0B634, /* Timesync Rx EtherType and Msg Type - RW */
E1000_RXUDP = 0x0B638, /* Timesync Rx UDP Port - RW */
};

#define E1000_DEV_ID_82571EB_COPPER 0x105E
#define E1000_DEV_ID_82571EB_FIBER 0x105F
#define E1000_DEV_ID_82571EB_SERDES 0x1060
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12 changes: 0 additions & 12 deletions drivers/net/ethernet/intel/e1000e/netdev.c
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Original file line number Diff line number Diff line change
Expand Up @@ -86,18 +86,6 @@ struct e1000_reg_info {
char *name;
};

#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */

#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */

static const struct e1000_reg_info e1000_reg_info_tbl[] = {

/* General Registers */
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