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yaml
---
r: 175612
b: refs/heads/master
c: 55d8a65
h: refs/heads/master
v: v3
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Paul Walmsley authored and paul committed Dec 11, 2009
1 parent eed24d9 commit c65aaca
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Showing 3 changed files with 17 additions and 15 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: 06b16939a3d58aa128fee22b9aaf7dbc9a5b7c1c
refs/heads/master: 55d8a65308a5099155683c5a9bba3b8577988111
14 changes: 0 additions & 14 deletions trunk/arch/arm/mach-omap2/clock34xx.c
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Expand Up @@ -322,22 +322,8 @@ static struct omap_clk omap34xx_clks[] = {

#define MAX_DPLL_WAIT_TRIES 1000000

#define MIN_SDRC_DLL_LOCK_FREQ 83000000

#define CYCLES_PER_MHZ 1000000

/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
#define SDRC_MPURATE_SCALE 8

/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
#define SDRC_MPURATE_BASE_SHIFT 9

/*
* SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
* 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
*/
#define SDRC_MPURATE_LOOPS 96

/*
* DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
* that are sourced by DPLL5, and both of these require this clock
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16 changes: 16 additions & 0 deletions trunk/arch/arm/mach-omap2/sdrc.h
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Expand Up @@ -56,4 +56,20 @@ static inline u32 sms_read_reg(u16 reg)
OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
#endif /* __ASSEMBLER__ */

/* Minimum frequency that the SDRC DLL can lock at */
#define MIN_SDRC_DLL_LOCK_FREQ 83000000

/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
#define SDRC_MPURATE_SCALE 8

/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
#define SDRC_MPURATE_BASE_SHIFT 9

/*
* SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
* 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
*/
#define SDRC_MPURATE_LOOPS 96


#endif

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