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yaml
---
r: 208575
b: refs/heads/master
c: cdf357f
h: refs/heads/master
i:
  208573: 8ec9b88
  208571: 447431c
  208567: f66cff4
  208559: 2bc7c68
  208543: 7e0da1c
  208511: ddb7fb5
v: v3
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Will Deacon authored and Russell King committed Aug 10, 2010
1 parent aa65dc0 commit c7ae969
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Showing 3 changed files with 21 additions and 1 deletion.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: 988257cfcbc468cb26b3addfcab1d0187c4e2399
refs/heads/master: cdf357f1e13a08a11261edacb3083746f65c1ed9
12 changes: 12 additions & 0 deletions trunk/arch/arm/Kconfig
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Expand Up @@ -1040,6 +1040,18 @@ config PL310_ERRATA_588369
is not correctly implemented in PL310 as clean lines are not
invalidated as a result of these operations. Note that this errata
uses Texas Instrument's secure monitor api.

config ARM_ERRATA_720789
bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
depends on CPU_V7 && SMP
help
This option enables the workaround for the 720789 Cortex-A9 (prior to
r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
As a consequence of this erratum, some TLB entries which should be
invalidated are not, resulting in an incoherency in the system page
tables. The workaround changes the TLB flushing routines to invalidate
entries regardless of the ASID.
endmenu

source "arch/arm/common/Kconfig"
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8 changes: 8 additions & 0 deletions trunk/arch/arm/include/asm/tlbflush.h
Original file line number Diff line number Diff line change
Expand Up @@ -378,7 +378,11 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
if (tlb_flag(TLB_V6_I_ASID))
asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
if (tlb_flag(TLB_V7_UIS_ASID))
#ifdef CONFIG_ARM_ERRATA_720789
asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
#else
asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
#endif

if (tlb_flag(TLB_BTB)) {
/* flush the branch target cache */
Expand Down Expand Up @@ -424,7 +428,11 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
if (tlb_flag(TLB_V6_I_PAGE))
asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
if (tlb_flag(TLB_V7_UIS_PAGE))
#ifdef CONFIG_ARM_ERRATA_720789
asm("mcr p15, 0, %0, c8, c3, 3" : : "r" (uaddr & PAGE_MASK) : "cc");
#else
asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
#endif

if (tlb_flag(TLB_BTB)) {
/* flush the branch target cache */
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