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ARM: S5P: Changes the definition name of default UART registers
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This patch changes the definition name of default UCON, ULCON, and
UFCON UART registers from ARCH(SoC) to Machine(Board). Because it
depends on machine.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Kukjin Kim committed Aug 5, 2010
1 parent 02a0456 commit c8def08
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Showing 7 changed files with 102 additions and 102 deletions.
30 changes: 15 additions & 15 deletions arch/arm/mach-s5p6440/mach-smdk6440.c
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Expand Up @@ -41,47 +41,47 @@
#include <plat/adc.h>
#include <plat/ts.h>

#define S5P6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)

#define S5P6440_ULCON_DEFAULT S3C2410_LCON_CS8
#define SMDK6440_ULCON_DEFAULT S3C2410_LCON_CS8

#define S5P6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
#define SMDK6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S3C2440_UFCON_TXTRIG16 | \
S3C2410_UFCON_RXTRIG8)

static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = S5P6440_UCON_DEFAULT,
.ulcon = S5P6440_ULCON_DEFAULT,
.ufcon = S5P6440_UFCON_DEFAULT,
.ucon = SMDK6440_UCON_DEFAULT,
.ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = SMDK6440_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = S5P6440_UCON_DEFAULT,
.ulcon = S5P6440_ULCON_DEFAULT,
.ufcon = S5P6440_UFCON_DEFAULT,
.ucon = SMDK6440_UCON_DEFAULT,
.ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = SMDK6440_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = S5P6440_UCON_DEFAULT,
.ulcon = S5P6440_ULCON_DEFAULT,
.ufcon = S5P6440_UFCON_DEFAULT,
.ucon = SMDK6440_UCON_DEFAULT,
.ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = SMDK6440_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = S5P6440_UCON_DEFAULT,
.ulcon = S5P6440_ULCON_DEFAULT,
.ufcon = S5P6440_UFCON_DEFAULT,
.ucon = SMDK6440_UCON_DEFAULT,
.ulcon = SMDK6440_ULCON_DEFAULT,
.ufcon = SMDK6440_UFCON_DEFAULT,
},
};

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24 changes: 12 additions & 12 deletions arch/arm/mach-s5p6442/mach-smdk6442.c
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Expand Up @@ -27,40 +27,40 @@
#include <plat/cpu.h>

/* Following are default values for UCON, ULCON and UFCON UART registers */
#define S5P6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
#define SMDK6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)

#define S5P6442_ULCON_DEFAULT S3C2410_LCON_CS8
#define SMDK6442_ULCON_DEFAULT S3C2410_LCON_CS8

#define S5P6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
#define SMDK6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4)

static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = S5P6442_UCON_DEFAULT,
.ulcon = S5P6442_ULCON_DEFAULT,
.ufcon = S5P6442_UFCON_DEFAULT,
.ucon = SMDK6442_UCON_DEFAULT,
.ulcon = SMDK6442_ULCON_DEFAULT,
.ufcon = SMDK6442_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = S5P6442_UCON_DEFAULT,
.ulcon = S5P6442_ULCON_DEFAULT,
.ufcon = S5P6442_UFCON_DEFAULT,
.ucon = SMDK6442_UCON_DEFAULT,
.ulcon = SMDK6442_ULCON_DEFAULT,
.ufcon = SMDK6442_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = S5P6442_UCON_DEFAULT,
.ulcon = S5P6442_ULCON_DEFAULT,
.ufcon = S5P6442_UFCON_DEFAULT,
.ucon = SMDK6442_UCON_DEFAULT,
.ulcon = SMDK6442_ULCON_DEFAULT,
.ufcon = SMDK6442_UFCON_DEFAULT,
},
};

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30 changes: 15 additions & 15 deletions arch/arm/mach-s5pc100/mach-smdkc100.c
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Expand Up @@ -44,47 +44,47 @@
#include <plat/iic.h>

/* Following are default values for UCON, ULCON and UFCON UART registers */
#define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
#define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)

#define S5PC100_ULCON_DEFAULT S3C2410_LCON_CS8
#define SMDKC100_ULCON_DEFAULT S3C2410_LCON_CS8

#define S5PC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
#define SMDKC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S3C2440_UFCON_RXTRIG8 | \
S3C2440_UFCON_TXTRIG16)

static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = S5PC100_UCON_DEFAULT,
.ulcon = S5PC100_ULCON_DEFAULT,
.ufcon = S5PC100_UFCON_DEFAULT,
.ucon = SMDKC100_UCON_DEFAULT,
.ulcon = SMDKC100_ULCON_DEFAULT,
.ufcon = SMDKC100_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = S5PC100_UCON_DEFAULT,
.ulcon = S5PC100_ULCON_DEFAULT,
.ufcon = S5PC100_UFCON_DEFAULT,
.ucon = SMDKC100_UCON_DEFAULT,
.ulcon = SMDKC100_ULCON_DEFAULT,
.ufcon = SMDKC100_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = S5PC100_UCON_DEFAULT,
.ulcon = S5PC100_ULCON_DEFAULT,
.ufcon = S5PC100_UFCON_DEFAULT,
.ucon = SMDKC100_UCON_DEFAULT,
.ulcon = SMDKC100_ULCON_DEFAULT,
.ufcon = SMDKC100_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = S5PC100_UCON_DEFAULT,
.ulcon = S5PC100_ULCON_DEFAULT,
.ufcon = S5PC100_UFCON_DEFAULT,
.ucon = SMDKC100_UCON_DEFAULT,
.ulcon = SMDKC100_ULCON_DEFAULT,
.ufcon = SMDKC100_UFCON_DEFAULT,
},
};

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30 changes: 15 additions & 15 deletions arch/arm/mach-s5pv210/mach-aquila.c
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Expand Up @@ -30,47 +30,47 @@
#include <plat/fb.h>

/* Following are default values for UCON, ULCON and UFCON UART registers */
#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)

#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8
#define AQUILA_ULCON_DEFAULT S3C2410_LCON_CS8

#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
#define AQUILA_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4)

static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = S5PV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT,
.ucon = AQUILA_UCON_DEFAULT,
.ulcon = AQUILA_ULCON_DEFAULT,
.ufcon = AQUILA_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = S5PV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT,
.ucon = AQUILA_UCON_DEFAULT,
.ulcon = AQUILA_ULCON_DEFAULT,
.ufcon = AQUILA_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = S5PV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT,
.ucon = AQUILA_UCON_DEFAULT,
.ulcon = AQUILA_ULCON_DEFAULT,
.ufcon = AQUILA_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = S5PV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT,
.ucon = AQUILA_UCON_DEFAULT,
.ulcon = AQUILA_ULCON_DEFAULT,
.ufcon = AQUILA_UFCON_DEFAULT,
},
};

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30 changes: 15 additions & 15 deletions arch/arm/mach-s5pv210/mach-goni.c
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Expand Up @@ -27,47 +27,47 @@
#include <plat/cpu.h>

/* Following are default values for UCON, ULCON and UFCON UART registers */
#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)

#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8
#define GONI_ULCON_DEFAULT S3C2410_LCON_CS8

#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
#define GONI_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4)

static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = S5PV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT,
.ucon = GONI_UCON_DEFAULT,
.ulcon = GONI_ULCON_DEFAULT,
.ufcon = GONI_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = S5PV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT,
.ucon = GONI_UCON_DEFAULT,
.ulcon = GONI_ULCON_DEFAULT,
.ufcon = GONI_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = S5PV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT,
.ucon = GONI_UCON_DEFAULT,
.ulcon = GONI_ULCON_DEFAULT,
.ufcon = GONI_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = S5PV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT,
.ucon = GONI_UCON_DEFAULT,
.ulcon = GONI_ULCON_DEFAULT,
.ufcon = GONI_UFCON_DEFAULT,
},
};

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30 changes: 15 additions & 15 deletions arch/arm/mach-s5pv210/mach-smdkc110.c
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Expand Up @@ -27,47 +27,47 @@
#include <plat/cpu.h>

/* Following are default values for UCON, ULCON and UFCON UART registers */
#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)

#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8
#define SMDKC110_ULCON_DEFAULT S3C2410_LCON_CS8

#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
#define SMDKC110_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4)

static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = S5PV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT,
.ucon = SMDKC110_UCON_DEFAULT,
.ulcon = SMDKC110_ULCON_DEFAULT,
.ufcon = SMDKC110_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = S5PV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT,
.ucon = SMDKC110_UCON_DEFAULT,
.ulcon = SMDKC110_ULCON_DEFAULT,
.ufcon = SMDKC110_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = S5PV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT,
.ucon = SMDKC110_UCON_DEFAULT,
.ulcon = SMDKC110_ULCON_DEFAULT,
.ufcon = SMDKC110_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = S5PV210_UCON_DEFAULT,
.ulcon = S5PV210_ULCON_DEFAULT,
.ufcon = S5PV210_UFCON_DEFAULT,
.ucon = SMDKC110_UCON_DEFAULT,
.ulcon = SMDKC110_ULCON_DEFAULT,
.ufcon = SMDKC110_UFCON_DEFAULT,
},
};

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