---

yaml
---
r: 147455
b: refs/heads/master
c: a4016a7
h: refs/heads/master
i:
  147453: 13407e6
  147451: dd80159
  147447: df72c8e
  147439: 335f59e
  147423: 26ac0b5
  147391: 63ffa2e
  147327: db52352
  147199: dd9b477
  146943: 5d9e81e
  146431: 943ba7b
  145407: 166de48
  143359: 808b3c9
  139263: 78d0ae8
  131071: 5e1d553
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 9e35ad388bea89f7d6f375af4c0ae98803688666
+refs/heads/master: a4016a79fcbd139e7378944c0d86a39fdbc70ecc

trunk/arch/x86/kernel/cpu/perf_counter.c

@@ -783,6 +783,10 @@ static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi)
 
 		counter = cpuc->counters[idx];
 		hwc = &counter->hw;
+
+		if (counter->hw_event.nmi != nmi)
+			goto next;
+
 		val = x86_perf_counter_update(counter, hwc, idx);
 		if (val & (1ULL << (x86_pmu.counter_bits - 1)))
 			goto next;
@@ -869,7 +873,6 @@ perf_counter_nmi_handler(struct notifier_block *self,
 {
 	struct die_args *args = __args;
 	struct pt_regs *regs;
-	int ret;
 
 	if (!atomic_read(&active_counters))
 		return NOTIFY_DONE;
@@ -886,9 +889,16 @@ perf_counter_nmi_handler(struct notifier_block *self,
 	regs = args->regs;
 
 	apic_write(APIC_LVTPC, APIC_DM_NMI);
-	ret = x86_pmu.handle_irq(regs, 1);
+	/*
+	 * Can't rely on the handled return value to say it was our NMI, two
+	 * counters could trigger 'simultaneously' raising two back-to-back NMIs.
+	 *
+	 * If the first NMI handles both, the latter will be empty and daze
+	 * the CPU.
+	 */
+	x86_pmu.handle_irq(regs, 1);
 
-	return ret ? NOTIFY_STOP : NOTIFY_OK;
+	return NOTIFY_STOP;
 }
 
 static __read_mostly struct notifier_block perf_counter_nmi_notifier = {