MIPS R2 instruction hazard handling.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
git-mirror · Oct 29, 2005 · cc61c1f · cc61c1f
1 parent bbc7f22
commit cc61c1f
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diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
@@ -529,6 +529,7 @@ static void r4k_flush_icache_range(unsigned long __user start,
 	args.end = end;
 
 	on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
+	instruction_hazard();
 }
 
 /*

diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
@@ -228,6 +228,22 @@ __asm__(
 
 #endif
 
+#if defined(CONFIG_CPU_MIPS32_R2) || defined (CONFIG_CPU_MIPS64_R2)
+#define instruction_hazard()						\
+do {									\
+__label__ __next;							\
+	__asm__ __volatile__(						\
+	"	jr.hb	%0					\n"	\
+	:								\
+	: "r" (&&__next));						\
+__next:									\
+	;								\
+} while (0)
+
+#else
+#define instruction_hazard() do { } while (0)
+#endif
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_HAZARDS_H */
-Original file line number
+Diff line change
@@ Expand Up @@
     	args.end = end;
     	on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
+    	instruction_hazard();
     }
     /*
@@ Expand Down @@