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drm/nv50-nvc0: initialise display sync channels
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Also imports a couple of helper functions that'll be used to implement
page flipping in the following commits..

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs committed Feb 24, 2011
1 parent 45c4e0a commit cdccc70
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Showing 6 changed files with 246 additions and 6 deletions.
2 changes: 2 additions & 0 deletions drivers/gpu/drm/nouveau/nouveau_dma.h
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Original file line number Diff line number Diff line change
Expand Up @@ -73,6 +73,8 @@ enum {
NvImageBlit = 0x8000000d,
NvSw = 0x8000000e,
NvSema = 0x8000000f,
NvEvoSema0 = 0x80000010,
NvEvoSema1 = 0x80000011,

/* G80+ display objects */
NvEvoVRAM = 0x01000000,
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22 changes: 21 additions & 1 deletion drivers/gpu/drm/nouveau/nouveau_object.c
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Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,7 @@
#include "nouveau_drm.h"
#include "nouveau_ramht.h"
#include "nouveau_vm.h"
#include "nv50_display.h"

struct nouveau_gpuobj_method {
struct list_head head;
Expand Down Expand Up @@ -782,7 +783,7 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_gpuobj *vram = NULL, *tt = NULL;
int ret;
int ret, i;

NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);

Expand Down Expand Up @@ -847,6 +848,25 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
nouveau_gpuobj_ref(NULL, &ramht);
if (ret)
return ret;

/* dma objects for display sync channel semaphore blocks */
for (i = 0; i < 2; i++) {
struct nouveau_gpuobj *sem = NULL;
struct nv50_display_crtc *dispc =
&nv50_display(dev)->crtc[i];
u64 offset = dispc->sem.bo->bo.mem.start << PAGE_SHIFT;

ret = nouveau_gpuobj_dma_new(chan, 0x3d, offset, 0xfff,
NV_MEM_ACCESS_RW,
NV_MEM_TARGET_VRAM, &sem);
if (ret)
return ret;

ret = nouveau_ramht_insert(chan, NvEvoSema0 + i, sem);
nouveau_gpuobj_ref(NULL, &sem);
if (ret)
return ret;
}
}

/* VRAM ctxdma */
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123 changes: 122 additions & 1 deletion drivers/gpu/drm/nouveau/nv50_display.c
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Original file line number Diff line number Diff line change
Expand Up @@ -178,7 +178,7 @@ nv50_display_init(struct drm_device *dev)

nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);

ret = RING_SPACE(evo, 11);
ret = RING_SPACE(evo, 15);
if (ret)
return ret;
BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
Expand All @@ -192,6 +192,11 @@ nv50_display_init(struct drm_device *dev)
OUT_RING(evo, 0);
BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
OUT_RING(evo, 0);
/* required to make display sync channels not hate life */
BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK900), 1);
OUT_RING (evo, 0x00000311);
BEGIN_RING(evo, 0, NV50_EVO_CRTC(1, UNK900), 1);
OUT_RING (evo, 0x00000311);
FIRE_RING(evo);
if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2))
NV_ERROR(dev, "evo pushbuf stalled\n");
Expand Down Expand Up @@ -366,6 +371,122 @@ nv50_display_destroy(struct drm_device *dev)
kfree(disp);
}

void
nv50_display_flip_stop(struct drm_crtc *crtc)
{
struct nv50_display *disp = nv50_display(crtc->dev);
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
struct nouveau_channel *evo = dispc->sync;
int ret;

ret = RING_SPACE(evo, 8);
if (ret) {
WARN_ON(1);
return;
}

BEGIN_RING(evo, 0, 0x0084, 1);
OUT_RING (evo, 0x00000000);
BEGIN_RING(evo, 0, 0x0094, 1);
OUT_RING (evo, 0x00000000);
BEGIN_RING(evo, 0, 0x00c0, 1);
OUT_RING (evo, 0x00000000);
BEGIN_RING(evo, 0, 0x0080, 1);
OUT_RING (evo, 0x00000000);
FIRE_RING (evo);
}

int
nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
struct nouveau_channel *chan)
{
struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
struct nv50_display *disp = nv50_display(crtc->dev);
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
struct nouveau_channel *evo = dispc->sync;
int ret;

ret = RING_SPACE(evo, 24);
if (unlikely(ret))
return ret;

/* synchronise with the rendering channel, if necessary */
if (likely(chan)) {
u64 offset = dispc->sem.bo->vma.offset + dispc->sem.offset;

ret = RING_SPACE(chan, 10);
if (ret) {
WIND_RING(evo);
return ret;
}

if (dev_priv->chipset < 0xc0) {
BEGIN_RING(chan, NvSubSw, 0x0060, 2);
OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
OUT_RING (chan, dispc->sem.offset);
BEGIN_RING(chan, NvSubSw, 0x006c, 1);
OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
BEGIN_RING(chan, NvSubSw, 0x0064, 2);
OUT_RING (chan, dispc->sem.offset ^ 0x10);
OUT_RING (chan, 0x74b1e000);
BEGIN_RING(chan, NvSubSw, 0x0060, 1);
if (dev_priv->chipset < 0x84)
OUT_RING (chan, NvSema);
else
OUT_RING (chan, chan->vram_handle);
} else {
BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
OUT_RING (chan, upper_32_bits(offset));
OUT_RING (chan, lower_32_bits(offset));
OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
OUT_RING (chan, 0x1002);
BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
OUT_RING (chan, upper_32_bits(offset));
OUT_RING (chan, lower_32_bits(offset ^ 0x10));
OUT_RING (chan, 0x74b1e000);
OUT_RING (chan, 0x1001);
}
FIRE_RING (chan);
} else {
nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4,
0xf00d0000 | dispc->sem.value);
}

/* queue the flip on the crtc's "display sync" channel */
BEGIN_RING(evo, 0, 0x0100, 1);
OUT_RING (evo, 0xfffe0000);
BEGIN_RING(evo, 0, 0x0084, 5);
OUT_RING (evo, chan ? 0x00000100 : 0x00000010);
OUT_RING (evo, dispc->sem.offset);
OUT_RING (evo, 0xf00d0000 | dispc->sem.value);
OUT_RING (evo, 0x74b1e000);
OUT_RING (evo, NvEvoSync);
BEGIN_RING(evo, 0, 0x00a0, 2);
OUT_RING (evo, 0x00000000);
OUT_RING (evo, 0x00000000);
BEGIN_RING(evo, 0, 0x00c0, 1);
OUT_RING (evo, nv_fb->r_dma);
BEGIN_RING(evo, 0, 0x0110, 2);
OUT_RING (evo, 0x00000000);
OUT_RING (evo, 0x00000000);
BEGIN_RING(evo, 0, 0x0800, 5);
OUT_RING (evo, (nv_fb->nvbo->bo.mem.start << PAGE_SHIFT) >> 8);
OUT_RING (evo, 0);
OUT_RING (evo, (fb->height << 16) | fb->width);
OUT_RING (evo, nv_fb->r_pitch);
OUT_RING (evo, nv_fb->r_format);
BEGIN_RING(evo, 0, 0x0080, 1);
OUT_RING (evo, 0x00000000);
FIRE_RING (evo);

dispc->sem.offset ^= 0x10;
dispc->sem.value++;
return 0;
}

static u16
nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
u32 mc, int pxclk)
Expand Down
15 changes: 15 additions & 0 deletions drivers/gpu/drm/nouveau/nv50_display.h
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Original file line number Diff line number Diff line change
Expand Up @@ -35,10 +35,21 @@
#include "nouveau_crtc.h"
#include "nv50_evo.h"

struct nv50_display_crtc {
struct nouveau_channel *sync;
struct {
struct nouveau_bo *bo;
u32 offset;
u16 value;
} sem;
};

struct nv50_display {
struct nouveau_channel *master;
struct nouveau_gpuobj *ntfy;

struct nv50_display_crtc crtc[2];

struct tasklet_struct tasklet;
struct {
struct dcb_entry *dcb;
Expand All @@ -62,6 +73,10 @@ void nv50_display_destroy(struct drm_device *dev);
int nv50_crtc_blank(struct nouveau_crtc *, bool blank);
int nv50_crtc_set_clock(struct drm_device *, int head, int pclk);

int nv50_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
struct nouveau_channel *chan);
void nv50_display_flip_stop(struct drm_crtc *);

int nv50_evo_init(struct drm_device *dev);
void nv50_evo_fini(struct drm_device *dev);
void nv50_evo_dmaobj_init(struct nouveau_gpuobj *, u32 memtype, u64 base,
Expand Down
88 changes: 84 additions & 4 deletions drivers/gpu/drm/nouveau/nv50_evo.c
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Original file line number Diff line number Diff line change
Expand Up @@ -220,7 +220,15 @@ static void
nv50_evo_destroy(struct drm_device *dev)
{
struct nv50_display *disp = nv50_display(dev);

int i;

for (i = 0; i < 2; i++) {
if (disp->crtc[i].sem.bo) {
nouveau_bo_unmap(disp->crtc[i].sem.bo);
nouveau_bo_ref(NULL, &disp->crtc[i].sem.bo);
}
nv50_evo_channel_del(&disp->crtc[i].sync);
}
nouveau_gpuobj_ref(NULL, &disp->ntfy);
nv50_evo_channel_del(&disp->master);
}
Expand All @@ -232,7 +240,7 @@ nv50_evo_create(struct drm_device *dev)
struct nv50_display *disp = nv50_display(dev);
struct nouveau_gpuobj *ramht = NULL;
struct nouveau_channel *evo;
int ret;
int ret, i, j;

/* create primary evo channel, the one we use for modesetting
* purporses
Expand Down Expand Up @@ -311,6 +319,61 @@ nv50_evo_create(struct drm_device *dev)
if (ret)
goto err;

/* create "display sync" channels and other structures we need
* to implement page flipping
*/
for (i = 0; i < 2; i++) {
struct nv50_display_crtc *dispc = &disp->crtc[i];
u64 offset;

ret = nv50_evo_channel_new(dev, 1 + i, &dispc->sync);
if (ret)
goto err;

ret = nouveau_bo_new(dev, NULL, 4096, 0x1000, TTM_PL_FLAG_VRAM,
0, 0x0000, false, true, &dispc->sem.bo);
if (!ret) {
offset = dispc->sem.bo->bo.mem.start << PAGE_SHIFT;

ret = nouveau_bo_pin(dispc->sem.bo, TTM_PL_FLAG_VRAM);
if (!ret)
ret = nouveau_bo_map(dispc->sem.bo);
if (ret)
nouveau_bo_ref(NULL, &dispc->sem.bo);
}

if (ret)
goto err;

ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoSync, 0x0000,
offset, 4096, NULL);
if (ret)
goto err;

ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoVRAM_LP, 0x80000000,
0, dev_priv->vram_size, NULL);
if (ret)
goto err;

ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB32, 0x80000000 |
(dev_priv->chipset < 0xc0 ?
0x7a00 : 0xfe00),
0, dev_priv->vram_size, NULL);
if (ret)
goto err;

ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB16, 0x80000000 |
(dev_priv->chipset < 0xc0 ?
0x7000 : 0xfe00),
0, dev_priv->vram_size, NULL);
if (ret)
goto err;

for (j = 0; j < 4096; j += 4)
nouveau_bo_wr32(dispc->sem.bo, j / 4, 0x74b1e000);
dispc->sem.offset = 0;
}

return 0;

err:
Expand All @@ -322,23 +385,40 @@ int
nv50_evo_init(struct drm_device *dev)
{
struct nv50_display *disp = nv50_display(dev);
int ret;
int ret, i;

if (!disp->master) {
ret = nv50_evo_create(dev);
if (ret)
return ret;
}

return nv50_evo_channel_init(disp->master);
ret = nv50_evo_channel_init(disp->master);
if (ret)
return ret;

for (i = 0; i < 2; i++) {
ret = nv50_evo_channel_init(disp->crtc[i].sync);
if (ret)
return ret;
}

return 0;
}

void
nv50_evo_fini(struct drm_device *dev)
{
struct nv50_display *disp = nv50_display(dev);
int i;

for (i = 0; i < 2; i++) {
if (disp->crtc[i].sync)
nv50_evo_channel_fini(disp->crtc[i].sync);
}

if (disp->master)
nv50_evo_channel_fini(disp->master);

nv50_evo_destroy(dev);
}
2 changes: 2 additions & 0 deletions drivers/gpu/drm/nouveau/nv50_evo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -113,5 +113,7 @@
/* Both of these are needed, otherwise nothing happens. */
#define NV50_EVO_CRTC_SCALE_RES1 0x000008d8
#define NV50_EVO_CRTC_SCALE_RES2 0x000008dc
#define NV50_EVO_CRTC_UNK900 0x00000900
#define NV50_EVO_CRTC_UNK904 0x00000904

#endif

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