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Merge tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/a…
…rm-soc Pull arm-soc power management changes from Olof Johansson: "Power management changes here are mostly for the omap platform, but also include cpuidle changes for ux500 and suspend/resume code for mmp." * tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits) ARM: OMAP2+: WDTIMER integration: fix !PM boot crash, disarm timer after hwmod reset ARM: OMAP2/3: hwmod data: Add 32k-sync timer data to hwmod database ARM: OMAP4: hwmod_data: Name the common irq for McBSP ports ARM: OMAP4: hwmod data: I2C: add flag for context restore ARM: OMAP3: hwmod_data: Rename the common irq for McBSP ports ARM: OMAP2xxx: hwmod data: add HDQ/1-wire hwmod ARM: OMAP3: hwmod data: add HDQ/1-wire hwmod ARM: OMAP2+: hwmod data: add HDQ/1-wire hwmod shared data ARM: OMAP2+: HDQ1W: add custom reset function ARM: OMAP2420: hwmod data: Add MMC hwmod data for 2420 arm: omap3: clockdomain data: Remove superfluous commas from gfx_sgx_3xxx_wkdeps[] ARM: OMAP2+: powerdomain: Get rid off duplicate pwrdm_clkdm_state_switch() API ARM: OMAP3: clock data: add clockdomain for HDQ functional clock ARM: OMAP3+: dpll: Configure autoidle mode only if it's supported ARM: OMAP2+: dmtimer: cleanup iclk usage ARM: OMAP4+: Add prm and cm base init function. ARM: OMAP2/3: Add idle_st bits for ST_32KSYNC timer to prcm-common header ARM: OMAP3: Fix CM register bit masks ARM: OMAP: clock: convert AM3517/3505 detection/flags to AM35xx ARM: OMAP3: clock data: treat all AM35x devices the same ...
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,61 @@ | ||
| /* | ||
| * MMP2 Power Management Routines | ||
| * | ||
| * This software program is licensed subject to the GNU General Public License | ||
| * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html | ||
| * | ||
| * (C) Copyright 2010 Marvell International Ltd. | ||
| * All Rights Reserved | ||
| */ | ||
|
|
||
| #ifndef __MMP2_PM_H__ | ||
| #define __MMP2_PM_H__ | ||
|
|
||
| #include <mach/addr-map.h> | ||
|
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||
| #define APMU_PJ_IDLE_CFG APMU_REG(0x018) | ||
| #define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1) | ||
| #define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5) | ||
| #define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16) | ||
| #define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19) | ||
| #define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28) | ||
|
|
||
| #define APMU_SRAM_PWR_DWN APMU_REG(0x08c) | ||
|
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||
| #define MPMU_SCCR MPMU_REG(0x038) | ||
| #define MPMU_PCR_PJ MPMU_REG(0x1000) | ||
| #define MPMU_PCR_PJ_AXISD (1 << 31) | ||
| #define MPMU_PCR_PJ_SLPEN (1 << 29) | ||
| #define MPMU_PCR_PJ_SPSD (1 << 28) | ||
| #define MPMU_PCR_PJ_DDRCORSD (1 << 27) | ||
| #define MPMU_PCR_PJ_APBSD (1 << 26) | ||
| #define MPMU_PCR_PJ_INTCLR (1 << 24) | ||
| #define MPMU_PCR_PJ_SLPWP0 (1 << 23) | ||
| #define MPMU_PCR_PJ_SLPWP1 (1 << 22) | ||
| #define MPMU_PCR_PJ_SLPWP2 (1 << 21) | ||
| #define MPMU_PCR_PJ_SLPWP3 (1 << 20) | ||
| #define MPMU_PCR_PJ_VCTCXOSD (1 << 19) | ||
| #define MPMU_PCR_PJ_SLPWP4 (1 << 18) | ||
| #define MPMU_PCR_PJ_SLPWP5 (1 << 17) | ||
| #define MPMU_PCR_PJ_SLPWP6 (1 << 16) | ||
| #define MPMU_PCR_PJ_SLPWP7 (1 << 15) | ||
|
|
||
| #define MPMU_PLL2_CTRL1 MPMU_REG(0x0414) | ||
| #define MPMU_CGR_PJ MPMU_REG(0x1024) | ||
| #define MPMU_WUCRM_PJ MPMU_REG(0x104c) | ||
| #define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x)) | ||
| #define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17) | ||
|
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||
| enum { | ||
| POWER_MODE_ACTIVE = 0, | ||
| POWER_MODE_CORE_INTIDLE, | ||
| POWER_MODE_CORE_EXTIDLE, | ||
| POWER_MODE_APPS_IDLE, | ||
| POWER_MODE_APPS_SLEEP, | ||
| POWER_MODE_CHIP_SLEEP, | ||
| POWER_MODE_SYS_SLEEP, | ||
| }; | ||
|
|
||
| extern void mmp2_pm_enter_lowpower_mode(int state); | ||
| extern int mmp2_set_wake(struct irq_data *d, unsigned int on); | ||
| #endif |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,77 @@ | ||
| /* | ||
| * PXA910 Power Management Routines | ||
| * | ||
| * This software program is licensed subject to the GNU General Public License | ||
| * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html | ||
| * | ||
| * (C) Copyright 2009 Marvell International Ltd. | ||
| * All Rights Reserved | ||
| */ | ||
|
|
||
| #ifndef __PXA910_PM_H__ | ||
| #define __PXA910_PM_H__ | ||
|
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||
| #define APMU_MOH_IDLE_CFG APMU_REG(0x0018) | ||
| #define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1) | ||
| #define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5) | ||
| #define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6) | ||
| #define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16) | ||
| #define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18) | ||
| #define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21) | ||
| #define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20) | ||
|
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| #define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c) | ||
| #define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0) | ||
|
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| #define MPMU_FCCR MPMU_REG(0x0008) | ||
| #define MPMU_APCR MPMU_REG(0x1000) | ||
| #define MPMU_APCR_AXISD (1 << 31) | ||
| #define MPMU_APCR_DSPSD (1 << 30) | ||
| #define MPMU_APCR_SLPEN (1 << 29) | ||
| #define MPMU_APCR_DTCMSD (1 << 28) | ||
| #define MPMU_APCR_DDRCORSD (1 << 27) | ||
| #define MPMU_APCR_APBSD (1 << 26) | ||
| #define MPMU_APCR_BBSD (1 << 25) | ||
| #define MPMU_APCR_SLPWP0 (1 << 23) | ||
| #define MPMU_APCR_SLPWP1 (1 << 22) | ||
| #define MPMU_APCR_SLPWP2 (1 << 21) | ||
| #define MPMU_APCR_SLPWP3 (1 << 20) | ||
| #define MPMU_APCR_VCTCXOSD (1 << 19) | ||
| #define MPMU_APCR_SLPWP4 (1 << 18) | ||
| #define MPMU_APCR_SLPWP5 (1 << 17) | ||
| #define MPMU_APCR_SLPWP6 (1 << 16) | ||
| #define MPMU_APCR_SLPWP7 (1 << 15) | ||
| #define MPMU_APCR_MSASLPEN (1 << 14) | ||
| #define MPMU_APCR_STBYEN (1 << 13) | ||
|
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| #define MPMU_AWUCRM MPMU_REG(0x104c) | ||
| #define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25) | ||
| #define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24) | ||
| #define MPMU_AWUCRM_SDH1 (1 << 23) | ||
| #define MPMU_AWUCRM_SDH2 (1 << 22) | ||
| #define MPMU_AWUCRM_KEYPRESS (1 << 21) | ||
| #define MPMU_AWUCRM_TRACKBALL (1 << 20) | ||
| #define MPMU_AWUCRM_NEWROTARY (1 << 19) | ||
| #define MPMU_AWUCRM_RTC_ALARM (1 << 17) | ||
| #define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13) | ||
| #define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12) | ||
| #define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11) | ||
| #define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10) | ||
| #define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9) | ||
| #define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8) | ||
| #define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7)) | ||
|
|
||
| enum { | ||
| POWER_MODE_ACTIVE = 0, | ||
| POWER_MODE_CORE_INTIDLE, | ||
| POWER_MODE_CORE_EXTIDLE, | ||
| POWER_MODE_APPS_IDLE, | ||
| POWER_MODE_APPS_SLEEP, | ||
| POWER_MODE_SYS_SLEEP, | ||
| POWER_MODE_HIBERNATE, | ||
| POWER_MODE_UDR, | ||
| }; | ||
|
|
||
| extern int pxa910_set_wake(struct irq_data *data, unsigned int on); | ||
|
|
||
| #endif |
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