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yaml
---
r: 205150
b: refs/heads/master
c: a2757b6
h: refs/heads/master
v: v3
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Zhenyu Wang authored and Eric Anholt committed Aug 2, 2010
1 parent 3e5d5ea commit ced7501
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Showing 3 changed files with 8 additions and 2 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: 3869d4a8afd3ce97770e66d6a96672af93984cc2
refs/heads/master: a2757b6fab6dee3dbf43bdb7d7226d03747fbdb1
6 changes: 6 additions & 0 deletions trunk/drivers/char/agp/intel-agp.h
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Expand Up @@ -60,6 +60,12 @@
#define I810_PTE_LOCAL 0x00000002
#define I810_PTE_VALID 0x00000001
#define I830_PTE_SYSTEM_CACHED 0x00000006
/* GT PTE cache control fields */
#define GEN6_PTE_UNCACHED 0x00000002
#define GEN6_PTE_LLC 0x00000004
#define GEN6_PTE_LLC_MLC 0x00000006
#define GEN6_PTE_GFDT 0x00000008

#define I810_SMRAM_MISCC 0x70
#define I810_GFX_MEM_WIN_SIZE 0x00010000
#define I810_GFX_MEM_WIN_32M 0x00010000
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2 changes: 1 addition & 1 deletion trunk/drivers/char/agp/intel-gtt.c
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Expand Up @@ -176,7 +176,7 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem,
if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
{
cache_bits = I830_PTE_SYSTEM_CACHED;
cache_bits = GEN6_PTE_LLC_MLC;
}

for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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