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yaml
---
r: 43000
b: refs/heads/master
c: 36b2a8d
h: refs/heads/master
v: v3
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Stephane Eranian authored and Andi Kleen committed Dec 7, 2006
1 parent ec53824 commit cf61be2
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Showing 3 changed files with 10 additions and 1 deletion.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: bd1d599518bf11992cc6d5b0df08da4a2b7b0db5
refs/heads/master: 36b2a8d5aff4cb3ee83d5e40447a8f073bcfe2fb
7 changes: 7 additions & 0 deletions trunk/arch/x86_64/kernel/setup.c
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Expand Up @@ -835,6 +835,13 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
}

if (cpu_has_ds) {
unsigned int l1, l2;
rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
if (!(l1 & (1<<12)))
set_bit(X86_FEATURE_PEBS, c->x86_capability);
}

n = c->extended_cpuid_level;
if (n >= 0x80000008) {
unsigned eax = cpuid_eax(0x80000008);
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2 changes: 2 additions & 0 deletions trunk/include/asm-x86_64/cpufeature.h
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Expand Up @@ -68,6 +68,7 @@
#define X86_FEATURE_FXSAVE_LEAK (3*32+7) /* FIP/FOP/FDP leaks through FXSAVE */
#define X86_FEATURE_UP (3*32+8) /* SMP kernel running on UP */
#define X86_FEATURE_ARCH_PERFMON (3*32+9) /* Intel Architectural PerfMon */
#define X86_FEATURE_PEBS (3*32+10) /* Precise-Event Based Sampling */

/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
Expand Down Expand Up @@ -113,5 +114,6 @@
#define cpu_has_centaur_mcr 0
#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS)
#define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS)

#endif /* __ASM_X8664_CPUFEATURE_H */

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