---

yaml
---
r: 324793
b: refs/heads/master
c: a498899
h: refs/heads/master
i:
  324791: 66cd8f5
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 564bbf9b4ab0dc147a358f3481bc616b5c650a4d
+refs/heads/master: a498899a3eb7cd4b180423e2cb2376f82d3d86c0

trunk/drivers/staging/ipack/devices/ipoctal.c

@@ -40,8 +40,8 @@ struct ipoctal {
 	struct list_head		list;
 	struct ipack_device		*dev;
 	unsigned int			board_id;
-	struct scc2698_channel		*chan_regs;
-	struct scc2698_block		*block_regs;
+	struct scc2698_channel __iomem	*chan_regs;
+	struct scc2698_block __iomem	*block_regs;
 	struct ipoctal_stats		chan_stats[NR_CHANNELS];
 	unsigned int			nb_bytes[NR_CHANNELS];
 	unsigned int			count_wr[NR_CHANNELS];
@@ -59,8 +59,8 @@ struct ipoctal {
 static LIST_HEAD(ipoctal_list);
 
 static inline void ipoctal_write_io_reg(struct ipoctal *ipoctal,
-					unsigned char *dest,
-					unsigned char value)
+					u8 __iomem *dest,
+					u8 value)
 {
 	iowrite8(value, dest);
 }
@@ -73,7 +73,7 @@ static inline void ipoctal_write_cr_cmd(struct ipoctal *ipoctal,
 }
 
 static inline unsigned char ipoctal_read_io_reg(struct ipoctal *ipoctal,
-						unsigned char *src)
+						u8 __iomem *src)
 {
 	return ioread8(src);
 }
@@ -391,9 +391,9 @@ static int ipoctal_inst_slot(struct ipoctal *ipoctal, unsigned int bus_nr,
 
 	/* Save the virtual address to access the registers easily */
 	ipoctal->chan_regs =
-		(struct scc2698_channel *) ipoctal->dev->io_space.address;
+		(struct scc2698_channel __iomem *) ipoctal->dev->io_space.address;
 	ipoctal->block_regs =
-		(struct scc2698_block *) ipoctal->dev->io_space.address;
+		(struct scc2698_block __iomem *) ipoctal->dev->io_space.address;
 
 	/* Disable RX and TX before touching anything */
 	for (i = 0; i < NR_CHANNELS ; i++) {

trunk/drivers/staging/ipack/devices/scc2698.h

@@ -23,21 +23,21 @@
 struct scc2698_channel {
 	union {
 		struct {
-			unsigned char d0, mr;  /* Mode register 1/2*/
-			unsigned char d1, sr;  /* Status register */
-			unsigned char d2, r1;  /* reserved */
-			unsigned char d3, rhr; /* Receive holding register (R) */
-			unsigned char junk[8]; /* other crap for block control */
-		} r; /* Read access */
+			u8 d0, mr;  /* Mode register 1/2*/
+			u8 d1, sr;  /* Status register */
+			u8 d2, r1;  /* reserved */
+			u8 d3, rhr; /* Receive holding register (R) */
+			u8 junk[8]; /* other crap for block control */
+		} __packed r; /* Read access */
 		struct {
-			unsigned char d0, mr;  /* Mode register 1/2 */
-			unsigned char d1, csr; /* Clock select register */
-			unsigned char d2, cr;  /* Command register */
-			unsigned char d3, thr; /* Transmit holding register */
-			unsigned char junk[8]; /* other crap for block control */
-		} w; /* Write access */
+			u8 d0, mr;  /* Mode register 1/2 */
+			u8 d1, csr; /* Clock select register */
+			u8 d2, cr;  /* Command register */
+			u8 d3, thr; /* Transmit holding register */
+			u8 junk[8]; /* other crap for block control */
+		} __packed w; /* Write access */
 	} u;
-};
+} __packed;
 
 /*
  * struct scc2698_block - Block access to scc2698 IO
@@ -50,43 +50,43 @@ struct scc2698_channel {
 struct scc2698_block {
 	union {
 		struct {
-			unsigned char d0, mra;  /* Mode register 1/2 (a) */
-			unsigned char d1, sra;  /* Status register (a) */
-			unsigned char d2, r1;   /* reserved */
-			unsigned char d3, rhra; /* Receive holding register (a) */
-			unsigned char d4, ipcr; /* Input port change register of block */
-			unsigned char d5, isr;  /* Interrupt status register of block */
-			unsigned char d6, ctur; /* Counter timer upper register of block */
-			unsigned char d7, ctlr; /* Counter timer lower register of block */
-			unsigned char d8, mrb;  /* Mode register 1/2 (b) */
-			unsigned char d9, srb;  /* Status register (b) */
-			unsigned char da, r2;   /* reserved */
-			unsigned char db, rhrb; /* Receive holding register (b) */
-			unsigned char dc, r3;   /* reserved */
-			unsigned char dd, ip;   /* Input port register of block */
-			unsigned char de, ctg;  /* Start counter timer of block */
-			unsigned char df, cts;  /* Stop counter timer of block */
-		} r; /* Read access */
+			u8 d0, mra;  /* Mode register 1/2 (a) */
+			u8 d1, sra;  /* Status register (a) */
+			u8 d2, r1;   /* reserved */
+			u8 d3, rhra; /* Receive holding register (a) */
+			u8 d4, ipcr; /* Input port change register of block */
+			u8 d5, isr;  /* Interrupt status register of block */
+			u8 d6, ctur; /* Counter timer upper register of block */
+			u8 d7, ctlr; /* Counter timer lower register of block */
+			u8 d8, mrb;  /* Mode register 1/2 (b) */
+			u8 d9, srb;  /* Status register (b) */
+			u8 da, r2;   /* reserved */
+			u8 db, rhrb; /* Receive holding register (b) */
+			u8 dc, r3;   /* reserved */
+			u8 dd, ip;   /* Input port register of block */
+			u8 de, ctg;  /* Start counter timer of block */
+			u8 df, cts;  /* Stop counter timer of block */
+		} __packed r; /* Read access */
 		struct {
-			unsigned char d0, mra;  /* Mode register 1/2 (a) */
-			unsigned char d1, csra; /* Clock select register (a) */
-			unsigned char d2, cra;  /* Command register (a) */
-			unsigned char d3, thra; /* Transmit holding register (a) */
-			unsigned char d4, acr;  /* Auxiliary control register of block */
-			unsigned char d5, imr;  /* Interrupt mask register of block  */
-			unsigned char d6, ctu;  /* Counter timer upper register of block */
-			unsigned char d7, ctl;  /* Counter timer lower register of block */
-			unsigned char d8, mrb;  /* Mode register 1/2 (b) */
-			unsigned char d9, csrb; /* Clock select register (a) */
-			unsigned char da, crb;  /* Command register (b) */
-			unsigned char db, thrb; /* Transmit holding register (b) */
-			unsigned char dc, r1;   /* reserved */
-			unsigned char dd, opcr; /* Output port configuration register of block */
-			unsigned char de, r2;   /* reserved */
-			unsigned char df, r3;   /* reserved */
-		} w; /* Write access */
+			u8 d0, mra;  /* Mode register 1/2 (a) */
+			u8 d1, csra; /* Clock select register (a) */
+			u8 d2, cra;  /* Command register (a) */
+			u8 d3, thra; /* Transmit holding register (a) */
+			u8 d4, acr;  /* Auxiliary control register of block */
+			u8 d5, imr;  /* Interrupt mask register of block  */
+			u8 d6, ctu;  /* Counter timer upper register of block */
+			u8 d7, ctl;  /* Counter timer lower register of block */
+			u8 d8, mrb;  /* Mode register 1/2 (b) */
+			u8 d9, csrb; /* Clock select register (a) */
+			u8 da, crb;  /* Command register (b) */
+			u8 db, thrb; /* Transmit holding register (b) */
+			u8 dc, r1;   /* reserved */
+			u8 dd, opcr; /* Output port configuration register of block */
+			u8 de, r2;   /* reserved */
+			u8 df, r3;   /* reserved */
+		} __packed w; /* Write access */
 	} u;
-} ;
+} __packed;
 
 #define MR1_CHRL_5_BITS             (0x0 << 0)
 #define MR1_CHRL_6_BITS             (0x1 << 0)